3-6 years of experience with strong knowledge in timing closure, IPI and system creation using Xilinx Vivado tool
Responsibilities include RTL development, resolving system level challenges, architecting, implementing, documenting and validating the memory controller IP cores.
Location : Hyderabad. * Pre and Post silicon Validation of PCIe based system * Writing/Modifying testcases in C and tcl * Develop new Vivado designs required for Validation * Debug with Chipscope and Lecroy Analyzer Developing IP's in Verilog/VHDL.
Job Description * Must be proactive in taking ownership of projects and problems, willing to take on challenging projects and open to creative solutions * Must be motivated to drive delivery and support of robust, high quality software * Tes
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