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3-6 years of experience with strong knowledge in timing closure, IPI and system creation using Xilinx Vivado tool

Skills :

RTL DESIGN, FPGA Design - VHDL, Verilog,,RF Design, System Verilog, PERL/Shell script ,OVM,UVM.

Company Name Confidential
Bengaluru / Bangalore Hyderabad / Secunderabad
4-8 years
250000 - 700000 INR

Responsibilities include RTL development, resolving system level challenges, architecting, implementing, documenting and validating the memory controller IP cores.

Skills :

FPGA Developer/Lead/Manager

Koral Human Resource Consultants
Hyderabad / Secunderabad
8-18 years
Not Specified

FPGA Developer/Lead/Manager

Skills :

Silicon Validation Engineer

Cadmaxx Solutions Private Limited
Hyderabad / Secunderabad
3-6 years
Not Specified

Location : Hyderabad. * Pre and Post silicon Validation of PCIe based system * Writing/Modifying testcases in C and tcl * Develop new Vivado designs required for Validation * Debug with Chipscope and Lecroy Analyzer Developing IP's in Verilog/VHDL.

Skills :

C++ Lead/SSE ; Product based MNC Hyderabad

Koral Human Resource Consultants
Hyderabad / Secunderabad
3-10 years
Not Specified

C++ Lead/SSE ; Product based MNC Hyderabad

Skills :

Principal Engineer, SQA

Microchip Technology India Private Limited
Hyderabad / Secunderabad
15-18 years
Not Specified

Job Description * Must be proactive in taking ownership of projects and problems, willing to take on challenging projects and open to creative solutions * Must be motivated to drive delivery and support of robust, high quality software * Tes

Skills :

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