Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
• Define and develop verification architecture and verification plan • Define and develop verification methodologies • Define and develop verification environments • Write verification specifications, verification plans, and documentation
Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification. Delivery of fully verified – including both functionally and test coverage.
Delivered with (as applicable) UVM, System Verilog, low power, SoC verification design flows, Functional & DFT Coverages Interfaced with designs/teams with embedded Analog design blocks Familiarity with Analog verification flows