verilog ams Jobs in Hyderabad

5+ years related proven silicon design or verification work experience.

Skills : analog simulators , Hspice , Finesim , Eldo , Questa ADMS , RNM , Verilog-AMS , silicon design , CAD , Verilog , System Verilog , Perl , Tcl

Minimum of 5+ years related proven silicon design or verification work experience.Hands on project experience with UVM verification methodologies

Skills : silicon design , UVM verification , systemverilog , Senior Engineer , Verilog , Tcl Scripting , Unix Shell Scripting , Perl

Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

Skills : Mixed signal Verification , Analog , virtuoso , Finseim , Hspice , Xcellium , simvision , Waveview , COSIM , Mixed signal verification , Verilog

Excellent opportunity | Design Verification | PAN India

Skills : Design Verification Engineer , Design Verification , Verification Engineer , IP / Sub-system verification , SV/ UVM , system interface protocols , IP verification project cycle , Testbench Strategies , TB development , simulation debugging

10+ years of related industry technical experience<br>

Skills : CMOS Circuit Design , Layout Design , Finesim , , Verilog , Python , Tcl , Perl

This position is a permanent position with our client (US Based Semiconductor Product Company with revenue more than 30 Billion USD). MS/PhD + 2 years or BS + 5years of experience in semiconductor industry.

Skills : Senior Datapath Design Engineer , Datapath , Digital Design , RTL , CMOS , Verilog

MS/PhD + 2 years or BS + 5years of experience in semiconductor industry.

Skills : Circuit Design Engineer , CMOS , RTL , Verilog , Scripting , Linux , Unix , Scripting

At least 7+ years’ experience in verification. Expertise in Building scalable HVL based verification environment from Scratch using System Verilog and OVM/UVM. <br>

Skills : VLSI DV Lead , HVL , Uvm , Verification , System Verilog , Ovm , Matlab

We Have Excellent Opportunity with ASIC Frontend Designer <br> Strong Exp in understanding, gathering and finalizing the requirements for ASIC/SOC design<br> Hands on experience in Verilog/VHDL/System.<br> Experience:- 7Y to10Y<br> Location:- HYD/Bang/Pune/Cochin.<br>

Skills : ASIC , Frontend Design , SOC design , Architecture , Micro-Architecture , ip design , Full Chip Integration , Digital Design , Boolean Arithmetic , Decoding , interfacing , Multi cook Designee , Setup Hold , clocking

10+yrs of expereince in ASIC Design. Expertise in understanding, gathering and finalizing the requirements for ASIC/SOC design.

Skills : VLSI ASIC Design Architect , ASIC Design , SOC design , ip design , VHDL , NCSim , cdc , Linting , Soc , Verilog , System Verilog , Static Timing Analysis

10+ years related proven silicon design or verification work experience

Skills : Principal Engineer , Verification , Uvm , VHDL , CAE tools , CAD Tools , Ovm , Hdl , System Verilog , Verilog , Unix Shell Scripting , Perl , Tcl Scripting

Minimum of 5+ years related proven silicon design or verification work experience

Skills : Principal Engineer , Uvm , AMBA , Firmware Verification , CMOS logic design , Circuit Design , Ovm , Pcie , Ethernet , System Verilog , Verilog

MS/PhD + 2 years or BS + 7years of experience in semiconductor industry.<br>

Skills : Array Design Tech lead , CMOS , FLASH array , Hspice , nand flash , Technical Leader , Verilog

6+ years relevant digital IP/SoC development experience

Skills : Senior Engineer II , Design , RTL , IP level , VHDL , ARM AMBA , Verilog , Uart , Gpio , I2c , Spi , System Verilog

Bachelors or Master’s Degree in Electrical/Electronics Engineering with a minimum of 10-12 yrs experience.

Skills : DSP algorithm designs , MatlabC , Simulink , FPGA design , VHDL , Verilog

Requires a Bachelors or Masters Degree in Electrical/Electronics Engineering with a minimum of 6-8 years experience.<br>

Skills : SFP Communications , MIPI , HDSI , MIPI , HDSI , VHDL , Verilog

Requires a Bachelors or Masters Degree in Electrical/Electronics Engineering with a minimum of 8-10 years experience.

Skills : Principal Engineer , RTL , MIPI , HDSI , display , VHDL , Fpga , Verilog

Minimum 7+years of experience in FPGA/RTL Design

Skills : Rtl Design , VHDL coding , Digital Design concepts , RTL Coding , FPGA tools flow , Xilinx , Altera , Xilinx FPGA , Zynq , Fpga , Verilog

Requires a Bachelors or Masters Degree in Electrical/Electronics Engineering with a minimum of 8-10 years experience.

Skills : Principal Engineer - Systems Solutions , MIPI , HDSI , display , VHDL programming , Verilog

12+ years of industry experience in semi-conductor industry

Skills : Lead Analog Design Engineer , Electrical Engineering , CMOS , Hspice , Fast SPICE , Cadence design , LVS , DRC Tools , Verilog , Linux , Unix

Experience managing the work assignments for a group of junior and senior engineers.11+ yrs of relevant work experienc

Skills : Principal Engineer , Validation , RTL Coding , VHDL , RTL , APB , AHB , Axi , Ace , Verilog

Bachelors or Master’s Degree in Electrical/Electronics Engineering (from a reputed University) with a minimum of 3-5 years’ experience in Semiconductor Industry.<br>

Skills : FPGA Design , VHDL , Acrobat , Dita , Verilog , Framemaker , MS Visio , Scripting , Xml

Minimum of 5+ years related proven silicon design or verification work experience.Hands on project experience with UVM verification methodologies

Skills : Staff Engineer , CAD , CDL , hspiceD , Cadence VXL , CAD , Design Automation , Fpga , Verilog , Perl , Python Scripting

Bachelors or Master’s Degree in Electrical/Electronics Engineering (from a reputed University) with a minimum of 2-4 years’ experience in Semiconductor Industry.<br>

Skills : FPGA Design , VHDL , FPGA Design engineer , Acrobat , Dita , Verilog , Framemaker , MS Visio , Scripting , Xml

BSEE (MSEE strongly preferred) and minimum of 10 years of industry experience.

Skills : Senior Engineer I - Design , test FPGA , VHDL , Verilog Coding , Voltage Reg , Pll , Testing , Scripting