• Define and develop verification architecture and verification plan • Define and develop verification methodologies • Define and develop verification environments • Write verification specifications, verification plans, and documentation
• Write verification specifications, verification plans, and documentation • Develop test bench and automate regression plans • Be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)
• Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification • Delivery of fully verified – including both functionally and test coverage w
Bachelor degree in a known university At least 10 years of proven experience in developing formal block level verification environments from scratch Experience with using Formal in the cluster Experience with latest formal techniques
• BS/MS in EE, CE, or CS with 5 - 10 Yrs of experience in Verification. • Experience in specifying and developing the verification infrastructure for verifying video based designs. • Strong analytical problem solving, and attention to details.