Floor planning/Power planning and Place and Route at block level and chip level,Clock Tree Synthesis, timing ecos and timing closure related PD activities,Integration of IO/Analog and Digital blocks,STA,TCL,PERLor PHYTON, physical verificationchecks
RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification. Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows.
Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
• Floor planning/Power planning and Place and Route at block level and chip level • Expert user of Synopsys ICC (or ICC2) – Floor-planning, Place & Route and Clock Tree Synthesis • In depth knowledge of CTS and customized clock implementations
They will be responsible for end to end Physical Design profile at our customer’s project(s) and should have prior experience in working on 10nm/7nm technology. In current set of projects they may have to work on 5nm/7nm technology
5+ years’ experience in physical implementation. Experience in all phases of the IC design process from RTL->GDS2 Physical implementation of SoC/Full-chip-level and/or high-speed CPU/GPU/DSP cores Experience in high-speed, low-power, mixed-signal So
10+years’ experience in chip implementation and 3-5 years as a technical lead/technical manager. Experience in all phases of the IC design process from RTL->GDS2 Physical implementation of SoC/Full-chip-leveland/or high-speed ARM/DSP/GPU cores Experi
Posted: 2 months ago
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