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tanner eda Jobs In bangalore

Urgent Opening //DFT Engineer//Bangalore MNC Client Hands on experience with DDR, CDC, DFT, MBIST, STA, LP checks, LEC. etc Front-End activities

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Urgent Opening //DFT Engineer//Bangalore MNC Client Hands on experience with DDR, CDC, DFT, MBIST, STA, LP checks, LEC. etc Front-End activities

Skills :

RTL Design Engineer for Product MNCs in Bangalore and Hyderabad

Cambio Consulting India Private Limited
Bengaluru / Bangalore Hyderabad / Secunderabad
4-12 years
Not Specified

ASIC RTL Design, CPU Design, SOC Design,Synthesis,STA,Lint,Verilog,System Verilog,Lint,Low power Design,Micro Architecture, CPU Architecture,Memory Controls,

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Physical Design Engineer

New Global Technologies
Bengaluru / Bangalore Hyderabad / Secunderabad
0-5 years
Not Specified

Physical Design Engineer

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DFT Engineer

Global Technologies
Bengaluru / Bangalore
5-14 years
Not Specified

5 to 12 yrs DFT experience including top-level hierarchical designs implementation experience. Strong hands on experience using Standard EDA Tools like Synopsys and Mentor. Strong understanding & hands on experience with industry standard DFT techniq

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DFT Engineer

Global Technologies
Bengaluru / Bangalore
5-14 years
Not Specified

5 to 12 yrs DFT experience including top-level hierarchical designs implementation experience. Strong hands on experience using Standard EDA Tools like Synopsys and Mentor. Strong understanding & hands on experience with industry standard DFT techniq

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Staff Engineer - Physical Design

Marvell India Private Limited
Bengaluru / Bangalore
10-15 years
Not Specified

10+ years of experience running an industry standard EDA tool for fullchip assembly and Physical Verification(LVS/DRC) is require

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Physical Design

Intel Technology India Private Limited
Bengaluru / Bangalore
7-17 years
Not Specified

We are looking for Structural Design Engineers with scope of work encompassing synthesis, scan, floor planning, auto place and route, clock tree synthesis, equivalency verification, static timing analysis, reliability and layout closure.

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Physical Design

Intel Technology India Private Limited
Bengaluru / Bangalore
7-17 years
Not Specified

We are looking for Structural Design Engineers with scope of work encompassing synthesis, scan, floor planning, auto place and route, clock tree synthesis, equivalency verification, static timing analysis, reliability and layout closure.

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Lead Design and Senior Lead Design Verification Engineer with PCIE/Ethernet/USB Protocol

Rafa International Private Limited
Bengaluru / Bangalore Hyderabad / Secunderabad
4-14 years
1600000 - 2200000 INR

PCIE/Ethernet/USB protocols,NVME sub-systems,developing UVM-based SV test-benches,defining block,sub-system & SOC top level test plans,ASIC simulation tools &advanced verification methods,debugging & problem solving,verification methodologies

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- LOGIC/RTL AISC/FPGA DESIGN & SIMULATION ENGINEER

Smart Iops (India) Research Center Private Limited
Bengaluru / Bangalore Thiruvananthapuram / Trivandrum
2-7 years
Not Specified

We have immediate requirement for Logic Design Engineers with 2-7 years of relevant experience.Performance Analysis,Micro-architecture design,block level specification,Synthesis/Implementation & Timing closure,Develop Test Plans

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Automation Engineer

Neugene International Solutions
Bengaluru / Bangalore
3-6 years
Not Specified

Automation Engineer with Python as language of expertise At least 3 years of experience in automation Should be having background of VLSI industry Added advantage if already worked in EDA domain (StdCell / Memory / IO characterization & EDA modelling

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Automation Engineer

Neugene International Solutions
Bengaluru / Bangalore
3-6 years
Not Specified

Automation Engineer with Python as language of expertise At least 3 years of experience in automation Should be having background of VLSI industry Added advantage if already worked in EDA domain (StdCell / Memory / IO characterization & EDA modelling

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6 to 10 years of experience in VLSI / RTL design.Experienced in Lint, CDC, logic synthesis, formal verification and static timing analysis.

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- LOGIC/RTL AISC/FPGA DESIGN & SIMULATION ENGINEER

Smart Iops (India) Research Center Private Limited
Bengaluru / Bangalore Thiruvananthapuram / Trivandrum
2-7 years
Not Specified

We have immediate requirement for Logic Design Engineers with 2-7 years of relevant experience.Performance Analysis,Micro-architecture design,block level specification,Synthesis/Implementation & Timing closure,Develop Test Plans

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Informatica MDM

Arminus Software Private Limited
Bengaluru / Bangalore
6-9 years
700000 - 1400000 INR

ETL Developer, DB Modeling,Informatica, MDM,

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Informatica MDM

Arminus Software Private Limited
Bengaluru / Bangalore
6-9 years
700000 - 1400000 INR

ETL Developer, DB Modeling,Informatica, MDM,

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STA Lead – Physical Design

PEOPLEplus Professional Services Pvt Ltd
Bengaluru / Bangalore
10-20 years
3000000 - 6500000 INR

Expertise in Static Timing Analysis tools (Primetime, Tempus) particularly constraints and exceptions - Prior experience converging large high-speed hierarchical designs - Experience with constraint-checking tools a plus 10-20yrs

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STA Lead – Physical Design

PEOPLEplus Professional Services Pvt Ltd
Bengaluru / Bangalore
10-20 years
3000000 - 6500000 INR

Expertise in Static Timing Analysis tools (Primetime, Tempus) particularly constraints and exceptions - Prior experience converging large high-speed hierarchical designs - Experience with constraint-checking tools a plus 10-20yrs

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I/O Layout Design Engineer

Wipro Limited
Bengaluru / Bangalore Hyderabad / Secunderabad
3-12 years
Not Specified

Custom layout development on block level to Top level I/O layout for LVCMOS, DDR, LVDS etc., Need knowledge on guard rings, latchup, ESD and EM.

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Memory Design

Wipro Limited
Bengaluru / Bangalore Hyderabad / Secunderabad
3-10 years
Not Specified

Design/verification of SRAM/RF/CAM custom/compiler memories in 7FF/16FF technologies

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IO Designer

Company Name Confidential
Bengaluru / Bangalore
4-14 years
Not Specified

Candidate is expected to have expertise in either Cadence, virtuoso, spectre, Mentor Calibre flows and should be capable of executing block or full chip level tasks independently.

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IO Designer

Company Name Confidential
Bengaluru / Bangalore
4-14 years
Not Specified

Candidate is expected to have expertise in either Cadence, virtuoso, spectre, Mentor Calibre flows and should be capable of executing block or full chip level tasks independently.

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Informatica MDM Developer

Capgemini Technology Services India Limited
Bengaluru / Bangalore
8-12 years
Not Specified

Experience in Informatica Master data Management.

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Informatica MDM Developer

Capgemini Technology Services India Limited
Bengaluru / Bangalore
8-12 years
Not Specified

Experience in Informatica Master data Management.

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