Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification. Delivery of fully verified – including both functionally and test coverage.
Delivered with (as applicable) UVM, System Verilog, low power, SoC verification design flows, Functional & DFT Coverages Interfaced with designs/teams with embedded Analog design blocks Familiarity with Analog verification flows
• 5-9 years functional verification experience in complex IP/SubSystem/SoCs in RTL and Gate level. • Hands on experience using an industry standard verification methodology (UVM/VMM). • Hands on experience on System Verilog •