We have an immediate opening in one of the Best MNCâ€™s in India for the Role of â€œSenior Research Associateâ€ for Bangalore Location having the largest process for CRO in India. The shifts are rotational.
We have an immediate opening in one of the Best MNC's in India for the Role of 'Clinical Research Associate' for Hyderabad Location having the largest process for Clinical research in India. The shifts are rotational.
Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.
As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to define the whole or
Floor planning/Power planning and Place and Route at block level and chip level,Clock Tree Synthesis, timing ecos and timing closure related PD activities,Integration of IO/Analog and Digital blocks,STA,TCL,PERLor PHYTON, physical verificationchecks
Posted: a month ago
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