Modify Search

Excellent Opportunity For Physical Designer Engineer & Lead

Stryde Consulting Services
Bengaluru / Bangalore Hyderabad / Secunderabad
2-12 years
Not Specified

Excellent Opportunity For Physical Designer Engineer<br> Strong Experience in Block level and sub-block floor-planning<br> Discuss SRAM placement with MediaTek PD team during block level floor-planning stage <br> Exp 5.0Yrs to 12.0Yrs<br> Loc :- Hyd/Bang/Pune<br>

Skills :

Physical Design Engineer and Lead

Wipro Limited
Bengaluru / Bangalore Hyderabad / Secunderabad
4-12 years
Not Specified

Routing and routing optimization for post-route timing and resolving congestion

Skills :

Power Design Engineer

Career Foresight Hr Solutions Llp
Bengaluru / Bangalore
3-10 years
500000 - 1000000 INR

Experience in Power Estimation, Power Grid Planning & Closure.<br> Experience in EM/IR Analysis and Signoff using Ansys Redhawk / Cadence Voltus tool<br> Block/Sub-system/SOC level IR Analysis (Static/Dynamic) and in-rush Analysis<br>

Skills :

BlockChain Developer

IT People Corporation LLC
Bengaluru / Bangalore Chennai
5-12 years
Not Specified

Candidates need to be very strong in Fabric, writing Chaincode using Golang, creating REST APIs using Node & Typescript, CI/CD, Dockers, Kubernetes, AWS.

Skills :

Full chip Physical design engineer

Vitestork Consulting Private Limited
Bengaluru / Bangalore
8-14 years
Not Specified

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills :

Design Engineer

Rapid Global Business Solutions India (P) Ltd
Bengaluru / Bangalore
2-5 years
Not Specified

Hiring Engineering graduate with 2-5 years experience in sub-system design (UG NX), OEM parts selection, CAD migration and NX Routing

Skills :

Physical Design Engineer

Vitestork Consulting Private Limited
Bengaluru / Bangalore
8-16 years
Not Specified

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills :

Physical design/STA Engineer

Vitestork Consulting Private Limited
Bengaluru / Bangalore
8-16 years
Not Specified

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.

Skills :

Sr. Cloud Architect GCP

Zensar Technologies Limited
Bengaluru / Bangalore Hyderabad / Secunderabad
15-18 years
Not Specified

15+ years of total experience. Atleast 2-3 projects recently worked on cloud

Skills :

CA Test Data Management lead -: -Immediate Opening with our Top MNC Client Bangalore/Chennai Location Location. <br>

Skills :

Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog. <br>

Skills :

Physical design Engineer

Vitestork Consulting Private Limited
Ahmedabad Bengaluru / Bangalore
4-10 years
Not Specified

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.

Skills :

Static Timing Analysis (STA)

Angel And Genie
Bengaluru / Bangalore
3-5 years
Not Specified

worked on hierarchical and block level STA analysis<br> <br> o good at debugging constraints and writing ECOs for timing fixes<br> <br> o must have worked on 10nm, 7nm, 5nm technology process nodes<br> <br> o should be familiar with DMSA or manual timing fixes

Skills :

Physical design Engineer

Vitestork Consulting Private Limited
Bengaluru / Bangalore
4-8 years
Not Specified

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes

Skills :

Full Chip Physical design Engineer/ STA

Vitestork Consulting Private Limited
Bengaluru / Bangalore
8-16 years
Not Specified

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis.

Skills :

Senior Engineer ASIC Design Verification

Micron Semiconductor Asia Operations Pte. Ltd
Bengaluru / Bangalore India
7-50 years
Not Specified

Req. ID: 249661 * * 7-years experience in UVM based ASIC verification * ASIC DV experience with UVM methodologies * Experience in developing UVM-based SV test-benches. * Experienced with defining block, sub-system or

Skills :

DFT Lead

Vitestork Consulting Private Limited
Ahmedabad Bengaluru / Bangalore
8-15 years
Not Specified

Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level

Skills :

Physical Design Engineer

Vitestork Consulting Private Limited
Ahmedabad Bengaluru / Bangalore
5-10 years
Not Specified

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal

Skills :

Principal Design Engineer

Cadence Design Systems (India) Pvt Ltd
Bengaluru / Bangalore India
Not Specified
Not Specified

Job Description : At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. *ASIC/Processor Design Verification position *Own all aspects of block/sub-system design-verification: *test-plan creatio

STA Engineer

Vitestork Consulting Private Limited
Ahmedabad Bengaluru / Bangalore
5-15 years
Not Specified

• Bachelor Degree in Engineering.<br> • Hands-on experience in defining and validating chip level as well as block leveling timing constraints.<br> • Well versed in setting up timing signoff flows<br>

Skills :

Excellent Opportunity with DFT Designer/Lead - HYD/BANG/Pune

Stryde Consulting Services
Bengaluru / Bangalore Hyderabad / Secunderabad
4-12 years
Not Specified

We have Excellent Opportunity with DFT Engineer /DFT Lead<br> Exp:- 5.0 Yrs to 12 Yrs. Locations:- HYD/Bang/Pune/Cochin<br> Strong in Design For Testing, Exp in Scan Insertion, Exp in ATPG

Skills :

ASIC Design Lead (Video Codec Design)

Qualcomm
Bengaluru / Bangalore
8-11 years
Not Specified

Company: Qualcomm India Private LimitedJob Area: Engineering Group, Engineering Group > Hardware EngineeringJob Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilit

Skills :

Know more