sub block Jobs in Bangalore

Excellent Opportunity For Physical Designer Engineer<br> Strong Experience in Block level and sub-block floor-planning<br> Discuss SRAM placement with MediaTek PD team during block level floor-planning stage <br> Exp 5.0Yrs to 12.0Yrs<br> Loc :- Hyd/Bang/Pune<br>

Skills : Physical Designer , Block Level , Sub Block , Sram , Clock Tree

Routing and routing optimization for post-route timing and resolving congestion

Skills : Physical Design Engineer , Physical Design Lead , Clean-up DRC error , Metal ECO , SPEF files Generation

Experience in Power Estimation, Power Grid Planning & Closure.<br> Experience in EM/IR Analysis and Signoff using Ansys Redhawk / Cadence Voltus tool<br> Block/Sub-system/SOC level IR Analysis (Static/Dynamic) and in-rush Analysis<br>

Skills : Power Design

Candidates need to be very strong in Fabric, writing Chaincode using Golang, creating REST APIs using Node & Typescript, CI/CD, Dockers, Kubernetes, AWS.

Skills : go language , go lang , Golang , Blockchain , Block Chain

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills : floorplanning , block partitioning , Power planning , CTS

Hiring Engineering graduate with 2-5 years experience in sub-system design (UG NX), OEM parts selection, CAD migration and NX Routing

Skills : sub system design , Hardware Design , oem parts selection , Engineering , Manufacturing , NX routing , Ugnx , Data Migration

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills : Floor Planning , Power planning , block partitioning

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.

Skills : Sta , Physical Design , Floor Planning , Place & route , Eco

15+ years of total experience. Atleast 2-3 projects recently worked on cloud

Skills : Cloud Bigquery , Cloud BigTable , Cloud Data Flow , Cloud Pub , Sub , ML APIs , Cloud MLc , AutoML , Gcp

Excellent opportunity | Design Verification | PAN India

Skills : Design Verification Engineer , Design Verification , Verification Engineer , IP / Sub-system verification , SV/ UVM , system interface protocols , IP verification project cycle , Testbench Strategies , TB development , simulation debugging

CA Test Data Management lead -: -Immediate Opening with our Top MNC Client Bangalore/Chennai Location Location. <br>

Skills : Data sub setting , and Data refresh for different data sources through the TDM tool , Data Profiling , data masking

Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog. <br>

Skills : Sta , VHDL , Vlsi , Static Timing Analysis , Verilog

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.

Skills : floorplanning , CTS , Sta , Physical Verification

worked on hierarchical and block level STA analysis<br> <br> o good at debugging constraints and writing ECOs for timing fixes<br> <br> o must have worked on 10nm, 7nm, 5nm technology process nodes<br> <br> o should be familiar with DMSA or manual timing fixes

Skills : Static Timing Analysis

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes

Skills : floorplanning , CTS , Sta , Physical Verification , Shell , Tcl , Perl , Python

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis.

Skills : ECO generation , ECO implemantation , power analysis

Req. ID: 249661 * * 7-years experience in UVM based ASIC verification * ASIC DV experience with UVM methodologies * Experience in developing UVM-based SV test-benches. * Experienced with defining block, sub-system or

Skills : Senior Engineer ASIC Design Verification

Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level

Skills : Dft , Scan Insertion , MBIST and JTAG , ATPG , Pattern validation , TetraMAX OR Cadence

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal

Skills : Floor Planning , CTS , Sta , Physical Verification

Job Description : At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. *ASIC/Processor Design Verification position *Own all aspects of block/sub-system design-verification: *test-plan creatio

Tamil & English Customer support

Skills : Telecaller , Call Center Executive , Voice Process , Customer Care Executive , Customer Support , Inbound , Outbound , Technical Support

Looking for Fullstack JAVA. 15+ years working experience in Eng Lead / Architect

Skills : Fullstack JAVA , PostrgreSQL , Swarm , block storage , Scaling , Azure Sql , Dockers , Kubernetes , Hybrid , Load Balancers , Networking , Scala , Python , Spark , Javascript , Reactjs , Devops , Agile

• Bachelor Degree in Engineering.<br> • Hands-on experience in defining and validating chip level as well as block leveling timing constraints.<br> • Well versed in setting up timing signoff flows<br>

Skills : Sta , ECO generation , , Static Timing Analysis

We have Excellent Opportunity with DFT Engineer /DFT Lead<br> Exp:- 5.0 Yrs to 12 Yrs. Locations:- HYD/Bang/Pune/Cochin<br> Strong in Design For Testing, Exp in Scan Insertion, Exp in ATPG

Skills : Dft , Design For Testing , Design For Testability , Scan Insertion , Synthesis , ATPG , Block/Device/ATPG

Company: Qualcomm India Private LimitedJob Area: Engineering Group, Engineering Group > Hardware EngineeringJob Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilit

Skills : ASIC Design Lead (Video Codec Design)