• 5-9 years functional verification experience in complex IP/SubSystem/SoCs in RTL and Gate level. • Hands on experience using an industry standard verification methodology (UVM/VMM). • Hands on experience on System Verilog •
8-12 yrs of RTL Design and Development using VHDL/Verilog, FPGA Design Experience in development of modules related to RF Front End, DSP algorithms in MATLAB related to MIMO/Beamforming,Experience in LTE or any OFDM based PHY module development.
• Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification • Delivery of fully verified – including both functionally and test coverage w