5+ years’ experience in physical implementation. Experience in all phases of the IC design process from RTL->GDS2 Physical implementation of SoC/Full-chip-level and/or high-speed CPU/GPU/DSP cores Experience in high-speed, low-power, mixed-signal So
Floor planning/Power planning and Place and Route at block level and chip level,Clock Tree Synthesis, timing ecos and timing closure related PD activities,Integration of IO/Analog and Digital blocks,STA,TCL,PERLor PHYTON, physical verificationchecks
We invite you to bring your expertise into play as you will provide the technical leadership to the team of Design engineers and CAD technicians for the projects assigned. To succeed in this role you must have BE/B. Tech degree in Civil Engineering.
8-12 yrs of RTL Design and Development using VHDL/Verilog, FPGA Design Experience in development of modules related to RF Front End, DSP algorithms in MATLAB related to MIMO/Beamforming,Experience in LTE or any OFDM based PHY module development.
Integrated in our Technology Enablement team,Especially in projects the Advanced Circuit Design (ACD) department will be driving. In close collaboration with other disciplines across our worldwide engineering teams you will be developing Analog Mixed