Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal
RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification. Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows.
Floor planning/Power planning and Place and Route at block level and chip level,Clock Tree Synthesis, timing ecos and timing closure related PD activities,Integration of IO/Analog and Digital blocks,STA,TCL,PERLor PHYTON, physical verificationchecks
Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.
As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge
IT Sourcer responsibilities include using various channels to look for potential candidates, contacting passive candidate and building talent pipelines for future hiring needs. If you have solid networking skills, know how to source on social media.
• Floor planning/Power planning and Place and Route at block level and chip level • Expert user of Synopsys ICC (or ICC2) – Floor-planning, Place & Route and Clock Tree Synthesis • In depth knowledge of CTS and customized clock implementations
5+ years’ experience in physical implementation. Experience in all phases of the IC design process from RTL->GDS2 Physical implementation of SoC/Full-chip-level and/or high-speed CPU/GPU/DSP cores Experience in high-speed, low-power, mixed-signal So
10+years’ experience in chip implementation and 3-5 years as a technical lead/technical manager. Experience in all phases of the IC design process from RTL->GDS2 Physical implementation of SoC/Full-chip-leveland/or high-speed ARM/DSP/GPU cores Experi