sta Jobs in Hyderabad

Proven experience in constraints (Func/Test) handling,

Skills : STA Manager , ECO generation , ECO implementation , power analysis , Constraints

A minimum with 12-16 years of total experience in RTL

Skills : Principal STA Engineer , rtl development , full chip STA , EDA Tools , RTL Coding , Coding , Perl

A minimum with 12-16 years of total experience in RTL

Skills : Principal STA Engineer , rtl development , full chip STA , EDA Tools , RTL Coding , Coding , Perl

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

Skills : Principal STA Engineer , rtl development , full chip STA , EDA Tools , RTL Coding , Coding , Perl

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

Skills : Principal STA Engineer , rtl development , full chip STA , EDA Tools , RTL Coding , Coding , Perl

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

Skills : Principal STA Engineer , rtl development , full chip STA , EDA Tools , RTL Coding , Coding , Perl

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

Skills : Senior STA & RTL Design Engineer , STA Engineer , Rtl Design Engineer , DRAM

A Bachelor in Electrical Engineering or related discipline plus 5 years of experience

Skills : RTL Design Engineer , EDA Tools , CAD , Modeling , Sta , RTL , Electrical Engineering

Under general supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design,Verification, Fabrication,Packaging of Chips

Skills : Physical Design Engineer , floorplanning , Power Grid Design , Placement , CTS , Sta , Power Integrity Analysis , Physical Verification , Chip finishing , Tk , Routing , Tcl , Perl

In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing.

Skills : Physical Design Engineer , floorplanning , Power Grid Design , Placement , CTS , Sta , Power Integrity Analysis , Physical Verification , Chip finishing , Tk , Routing , Tcl , Perl

In-depth knowledge and hands-on experience on Netlist2GDSII Implementation

Skills : Physical Design Technical Lead , floorplanning , Power Grid Design , Placement , CTS , Sta , Power Integrity Analysis , Physical Verification , Chip finishing , Tk , Routing , Tcl , Perl

Req. ID: 221205 Job Description As a Design Engineer in DRAM and Emerging memory Group (DEG), you will be responsible for designing and verifying Functional Blocks used in the development of memory products. This includes simulating, optimizing, and

Skills : STA Engineer

Req. ID: 231001Responsibilities include, but not limited to: * Hands-on write constraints for designs with complex clock structures * Constraint& mode reduction, own design timing across functions * Drive Design margins * Setup distribute

Skills : Principal STA Engineer

Job Description : Job Description As a Design Engineer in DRAM and Emerging memory Group (DEG), you will be responsible for designing and verifying Functional Blocks used in the development of memory products. This includes simulating, optimizing, a

Skills : Manufacturing Engineer , Engineer , Electrical , CAD , Drafting , Engineering

Job Description : Responsibilities include, but not limited to: * Hands-on write constraints for designs with complex clock structures * Constraint& mode reduction, own design timing across functions * Drive Design margins * Setup distrib

Skills : Engineer , Compliance , Engineering , Legal

Job Description : Micron Technology’s vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader i

Skills : Manufacturing Engineer , Engineer , Electrical , Computer Science , Compliance , Engineering , Technology , Legal

Job Description : Job Description As a Design Engineer in DRAM and Emerging memory Group (DEG), you will be responsible for designing and verifying Functional Blocks used in the development of memory products. This includes simulating, optimizing, a

Skills : Manufacturing Engineer , Electrical , Engineer , CAD , Drafting , Engineering

Req. ID: 239781 Micron Technology’s vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in m

Skills : Principal STA Engineer

Req. ID: 262661 Job Description As a Design Engineer in DRAM and Emerging memory Group (DEG), you will be responsible for designing and verifying Functional Blocks used in the development of memory products. This includes simulating, optimizing, and

Skills : Staff/Principal Engineer -STA

Job Description : Job requirements/Qualifications: * A minimum with 10-14 years of total experience in full chip constraint development, Synthesis and STA * Strong Synthesis and STA fundamentals. * Must have proven experience constraint crea

Skills : Engineer , Compliance , Engineering , Legal

Req. ID: 243221Job requirements/Qualifications: * A minimum with 10-14 years of total experience in full chip constraint development, Synthesis and STA * Strong Synthesis and STA fundamentals. * Must have proven experience constraint creatio

Skills : ASIC Synthesis/STA - Principal Engineer

Company: Qualcomm India Private LimitedJob Area: Engineering Group, Engineering Group > Hardware EngineeringJob Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilit

Skills : SoC Design/Synthesis/STA/ Low-Power Careers @ Qualcomm , Hyderabad , (3-18yrs exp)

In this role as a Senior DFT Engineer you will performs DFT implementation and verification activities of complex SoCs/ASICS by collaborating with cross functional teams and architects.

Skills : Senior DFT Engineer , DFT implementation , SoCs , ASICS , Scan Insertion , DRC , coverage analysis , DFT EDA tools , Perl , Tcl

In this role as a DFT Technical Lead you will performs DFT implementation and verification activities of complex SoCs/ASICS by collaborating with cross functional teams and architects

Skills : DFT Technical Lead , full chip DFT design , vector generation , Verification , boundary scan , ATPG , ASIC Design , Jtag , Soc

In this role as DFT Project Manager you will be leading all the DFT activities and deliverables of DFT teams & Customers at Cyient. You will be responsible for DFT Team management, Customer interactions and Engineering work which includes DFT

Skills : DFT lead , DFT Project Manager , Test Architecture , Stuck-At , Compression , ATPG , MBIST , BSCAN , DFT tools , Jtag