sta Jobs in Bengaluru bangalore

As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge

Skills : CAD Engineer , Cadence Tempus , Synopsys PT-SI , SDC linting , EDA tool , Tcl Scripting

worked on hierarchical and block level STA analysis<br> <br> o good at debugging constraints and writing ECOs for timing fixes<br> <br> o must have worked on 10nm, 7nm, 5nm technology process nodes<br> <br> o should be familiar with DMSA or manual timing fixes

Skills : Static Timing Analysis

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.

Skills : Sta , Physical Design , Floor Planning , Place & route , Eco

• Bachelor Degree in Engineering.<br> • Hands-on experience in defining and validating chip level as well as block leveling timing constraints.<br> • Well versed in setting up timing signoff flows<br>

Skills : Sta , ECO generation , , Static Timing Analysis

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis.

Skills : ECO generation , ECO implemantation , power analysis

3 to 5 years of experience in synthesis, STA and timing closure<br> <br>

Skills : Synthesis , Sta , Synopsys , Cadence Tools , Synopsys DC , PT tools , VHDL , Static Timing Analysis , Verilog , Perl , Tcl , Shell Script

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

Skills : Principal STA Engineer , rtl development , full chip STA , EDA Tools , RTL Coding , Coding , Perl

Role Summary: With an installed base of over 40 Enterprise customers, Company is now looking <br> to induct a Technology Practice Leader, who will enable delivery scalability. He / She should lead <br>

Skills : Communication Skills , Performance Engineering , Cassandra , J2EE , Struts , Ejb , Java , Technical Architect , Spring , Websphere , Jboss , Weblogic , RDBMS , Sql , Mysql , Mssql , Jms , Agile Methodology , Oracle , MongoDB , Dynatrace , Ejb , Appdynamics , Continous Integration , Jsf

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal

Skills : Floor Planning , CTS , Sta , Physical Verification

Dear Candidate<br> <br> Greetings from Kiash Solutions!!!<br> <br> <br> <br> We have opportunity with one of the leading Semiconductor Organization. for Physical Design Engineer for Bangalore, Ahemadabad Location .Please find the jd for your reference. Kindly got through

Skills : Physical Design , Sta , Physical Design Engineer , Signoff , cts , Sta , Physical Verification

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.

Skills : floorplanning , CTS , Sta , Physical Verification

Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog. <br>

Skills : Sta , VHDL , Vlsi , Static Timing Analysis , Verilog

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes

Skills : floorplanning , CTS , Sta , Physical Verification , Shell , Tcl , Perl , Python

Notice Period: Max upto 20 days<br> <br> Work Location:<br> 23-56P, Devarabeesanahalli<br> Varthur Hobli, Outer Ring Road<br> Bengaluru<br> Karnataka<br> <br> Description:<br> <br> CW will assist the DE Leads in executing structural design (Physical Design) including Synthesis runs, P&R, A

Skills : ynopsys Design Compiler , ICCII , ICV , PrimeTime (for STA) , Synopsys Lynx Environment , Cadence INNOVUS , and scripting in TCL , PERL

Hands-on technical ownership of SoC for top-down/bottom-up physical design integration

Skills : Physical Design Engineer , physical design integration , STA analysis , IVD , EM analysis

Floor planning/Power planning and Place and Route at block level and chip level Expert user of Synopsys ICC (or ICC2)

Skills : Physical Design , PNR ( Place and Route ) , ICC , Sta , Synthesis

Floor planning/Power planning and Place and Route at block level and chip level,Clock Tree Synthesis, timing ecos and timing closure related PD activities,Integration of IO/Analog and Digital blocks,STA,TCL,PERLor PHYTON, physical verificationchecks

Skills : Principal / Staff Physical Design Engineer - synthesisplacementrtl to gds"place & route"pnrsta"timing closure""timing analysis"netlistgdsfloorplaning"floor planing""ir drop"chiproute

In this role as a Senior DFT Engineer you will performs DFT implementation and verification activities of complex SoCs/ASICS by collaborating with cross functional teams and architects.

Skills : Senior DFT Engineer , DFT implementation , SoCs , ASICS , Scan Insertion , DRC , coverage analysis , DFT EDA tools , Perl , Tcl

They will be responsible for end to end Physical Design profile at our customer’s project(s) and should have prior experience in working on 10nm/7nm technology. In current set of projects they may have to work on 5nm/7nm technology

Skills : Physical Design Lead , Physical Design Manager , Physical Design , Floor Planning , Placement , CTS , crosstalk avoidance , Physical Verification , routing

In this role as a DFT Technical Lead you will performs DFT implementation and verification activities of complex SoCs/ASICS by collaborating with cross functional teams and architects

Skills : DFT Technical Lead , full chip DFT design , vector generation , Verification , boundary scan , ATPG , ASIC Design , Jtag , Soc

In this role as DFT Project Manager you will be leading all the DFT activities and deliverables of DFT teams & Customers at Cyient. You will be responsible for DFT Team management, Customer interactions and Engineering work which includes DFT

Skills : DFT lead , DFT Project Manager , Test Architecture , Stuck-At , Compression , ATPG , MBIST , BSCAN , DFT tools , Jtag

We are looking for Physical Design Lead/Manager with 8 to 15 years of experience on:<br> <br> · They will be responsible for end to end Physical Design profile at our customer’s project(s) and should have prior experience in working on 10nm/7nm technology.

Skills : Physical Design

Expertise in ASIC design implementation flow and hierarchical physical design strategies, methodologies<br> <br>

Skills : Physical Design Engineer , ASIC Design , Dft , Tcl , Perl , Scripting

Looking for Principal DFT Engineer

Skills : Dft , Dft Engineer , Synopsys , Cadenc , Mentor Graphics Tools

Work at various levels of implementation of hierarchical chip (Blocks and Top)

Skills : Senior Physical Design Engineer , Physical Design Engineer , Vlsi , EDA Tool , Innovus , Tempus , PrimeTime-SI , Voltus , redhawk , StarXT , Quantus , Calibre , LEC , python , Tcl