In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal
Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.
As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge
IT Sourcer responsibilities include using various channels to look for potential candidates, contacting passive candidate and building talent pipelines for future hiring needs. If you have solid networking skills, know how to source on social media.
Under general supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design,Verification, Fabrication,Packaging of Chips
In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing.
Require a enthusiastic candidate who is willing to work with dedication and honesty for mapping Tankers in operation. *Candidate should be having 3 year experience in Dairy Industry. *Candidate should be willing to shift anywhere with in the UP sta
• Floor planning/Power planning and Place and Route at block level and chip level • Expert user of Synopsys ICC (or ICC2) – Floor-planning, Place & Route and Clock Tree Synthesis • In depth knowledge of CTS and customized clock implementations