soc ic block Jobs in Hyderabad

work with design team to develop power islands for 16G serdes , setup UPF flow for SOC IC Block, come up with design guidelines.

Skills : Senior Design Verification Engineer , power pro , PTPX , EDA Tools , SOC IC Block , RTL

Experience in SOC Verification<br> <br> ·         Experience in UVM/SV based verification methodology is must<br> <br> ·         Candidates with CPU-Core, Peripherals, Low Power Verification or Modem domain are preferred.

Skills : SoC Verification

<br> Requirements:<br> • 2+ years of experience as a SOC Engineer<br> • 1 + Years of experience in Information Security or Networking required<br> • 1+ years of experience with at least one of the following technologies;<br>

Skills : SOC Engineer

Production System health and Alert monitoring with correlation in mind to figure out any progressive or sudden discrepancy.

Skills : SOC Engineer , System On a Chip , Soc

Candidates need to be very strong in Fabric, writing Chaincode using Golang, creating REST APIs using Node & Typescript, CI/CD, Dockers, Kubernetes, AWS.

Skills : go language , go lang , Golang , Blockchain , Block Chain

• Write verification specifications, verification plans, and documentation<br> • Develop test bench and automate regression plans<br> • Be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)<br>

Skills : Asic verification , RTL , Soc , Verilog

In this role as a DFT Technical Lead you will performs DFT implementation and verification activities of complex SoCs/ASICS by collaborating with cross functional teams and architects

Skills : DFT Technical Lead , full chip DFT design , vector generation , Verification , boundary scan , ATPG , ASIC Design , Jtag , Soc

• Define and develop verification architecture and verification plan<br> • Define and develop verification methodologies<br> • Define and develop verification environments<br> • Write verification specifications, verification plans, and documentation<br>

Skills : ASIC , Asic verification , RTL , VHDL , Soc , Verilog

Block Chain Developer

Skills : Qt Widgets module , Stl , C++11

Experienced in handling incident investigations independently.5-7 years of experience in working with any leading SIEM tools like Splunk, Qradar, LogRhythm, ArcSight, Perimeter devices like firewalls, routers, IDS/IPS etc.

Skills : , Soc , Siem

Excellent Opportunity For Physical Designer Engineer<br> Strong Experience in Block level and sub-block floor-planning<br> Discuss SRAM placement with MediaTek PD team during block level floor-planning stage <br> Exp 5.0Yrs to 12.0Yrs<br> Loc :- Hyd/Bang/Pune<br>

Skills : Physical Designer , Block Level , Sub Block , Sram , Clock Tree

Experience working with Ruby on Rails development the Block Chain POS and <br> Applications

Skills : Block chain" , "ror"

Required solution Architect with at least 1 Go Project experience on Blockchain.<br> Looking for candidates with Strong knowledge on ethereum Blockchain and smart contracts along with Strong software development background.<br>

Skills : Solution Architect , Block Chain , Cloud , AWS , Ethereum

10+ Years Experience working within standardization bodies is a big plus

Skills : ASIC/SoC design , M-PHY , UniPro , SERDES , eMMC , UFS , NAND , NAND Standards Engineer , Pcie , Scsi , Nvme

We have Excellent Opportunity with DFT Engineer /DFT Lead<br> Exp:- 5.0 Yrs to 12 Yrs. Locations:- HYD/Bang/Pune/Cochin<br> Strong in Design For Testing, Exp in Scan Insertion, Exp in ATPG

Skills : Dft , Design For Testing , Design For Testability , Scan Insertion , Synthesis , ATPG , Block/Device/ATPG

MSEE with 3-5 years of experience in product characterization or silicon validation with emphasis on digital and mixed-signal

Skills : FPGA Architectures , Xilinx , Altera , quartus , Pll , Oscillators , VHDL , Pll , Oscillators , Soc , Verilog , Silicon Validation , Soc

Strong Experience in Physical Design & Physical Verification.<br> Working experience with tools like ICC2/ Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.<br> Proficiency using Perl,Tcl,Pytho<br> Exp:- 4Yrs to 12 Yrs, Location:- HYD/Bang/Pune

Skills : Physical Design , Physical Verification , RTL2GDS , 16nm , 10nm , 7nm , Synthesis , Block Level , ICC2 , / Innovus , Primetime/Tempus , ICC2 , Synopsys

10+yrs of expereince in ASIC Design. Expertise in understanding, gathering and finalizing the requirements for ASIC/SOC design.

Skills : VLSI ASIC Design Architect , ASIC Design , SOC design , ip design , VHDL , NCSim , cdc , Linting , Soc , Verilog , System Verilog , Static Timing Analysis

8-12 years of experience in product characterization or silicon validation with emphasis on digital and mixed-signal

Skills : Pll , Oscillators , logic analyzers , spectrum analyzers , Oscilloscopes , function generators , VHDL , FPGA Architectures , Soc , Verilog

We Have Excellent Opportunity with ASIC Frontend Designer <br> Strong Exp in understanding, gathering and finalizing the requirements for ASIC/SOC design<br> Hands on experience in Verilog/VHDL/System.<br> Experience:- 7Y to10Y<br> Location:- HYD/Bang/Pune/Cochin.<br>

Skills : ASIC , Frontend Design , SOC design , Architecture , Micro-Architecture , ip design , Full Chip Integration , Digital Design , Boolean Arithmetic , Decoding , interfacing , Multi cook Designee , Setup Hold , clocking

Hands on experience in testing and debug of silicon (such as FPGA, ASIC, test chips, etc.)

Skills : Software Test Engineer , Test Development , ASIC , test chips , C+ , VHDL , teradyne j750 , Silicon Validation , Fpga , Java , C++ , Verilog , Java Programming , Soc

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills : Senior Verification engineer , Verification Engineer , SV-OVM , RTL , AHB , Axi , Architectural Design , Circuit Design , Physical Design , Verification , Fabrication , System Verilog , Perl , Tcl , Logic Design

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills : SV-OVM , RTL , AHB , Axi , Verification , RTL , Lead Engineer , System Verilog , Pci , Perl , Tcl , Verilog

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills : RAL , Uvm , Digital Verification , RTL , AHB , Axi , Associate Project Manager , System Verilog , Perl , Tcl , Usb , Ethernet

10+ years related proven silicon design or verification work experience

Skills : Principal Engineer , Verification , Uvm , VHDL , CAE tools , CAD Tools , Ovm , Hdl , System Verilog , Verilog , Unix Shell Scripting , Perl , Tcl Scripting