signoff Jobs in Bangalore

Dear Candidate<br> <br> Greetings from Kiash Solutions!!!<br> <br> <br> <br> We have opportunity with one of the leading Semiconductor Organization. for Physical Design Engineer for Bangalore, Ahemadabad Location .Please find the jd for your reference. Kindly got through

Skills : Physical Design , Sta , Physical Design Engineer , Signoff , cts , Sta , Physical Verification

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.

Skills : floorplanning , CTS , Sta , Physical Verification

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes

Skills : floorplanning , CTS , Sta , Physical Verification , Shell , Tcl , Perl , Python

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills : floorplanning , block partitioning , Power planning , CTS

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal

Skills : Floor Planning , CTS , Sta , Physical Verification

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills : Floor Planning , Power planning , block partitioning

SAP EHS Functional Consultant

Skills : "SAP EHS" , "SAP EHSM" , "SAP EHS Functional" , "SAP EHSM Functional" , "SAP EH&S"

• Bachelor Degree in Engineering.<br> • Hands-on experience in defining and validating chip level as well as block leveling timing constraints.<br> • Well versed in setting up timing signoff flows<br>

Skills : Sta , ECO generation , , Static Timing Analysis

As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge

Skills : CAD Engineer , Cadence Tempus , Synopsys PT-SI , SDC linting , EDA tool , Tcl Scripting

Experience in Power Estimation, Power Grid Planning & Closure.<br> Experience in EM/IR Analysis and Signoff using Ansys Redhawk / Cadence Voltus tool<br> Block/Sub-system/SOC level IR Analysis (Static/Dynamic) and in-rush Analysis<br>

Skills : Power Design

Looking for Physical Design/ Structural Design Engineers with scope of work encompassing synthesis, scan, floor planning, auto place and route, clock tree synthesis, equivalency verification, static timing analysis, reliability and layout closure.

Skills : Physical Design , Structural Design Engineers , RTL , ASIC integration , Vlsi , EDA Tools , Synopsys , CAD Tools , ASIC integration , Cadence , Mentor Graphic , Floor Planning tools , Perl , Python

Procurement Manager

Skills : Procurement Manager , BOQ Estimates , Quotation , price margin , Procurement Management , Pr , Rfq , Vendor Selection , Payment , cost break-up , Evaluation , Inventory , Life Cycle Analysis , Cost analysis. , Po

Roles and Responsibilities * BS/MS in EE/CS with 5+ years of hands-on experience inSignoff STA, extraction, andtiming ECO flowsand methodology. * Recent experience with either Cadence Tempus or SynopsysPT-SI (experience withboth is a plus). So

Skills : Eco , Sta , Signoff , Timing Analysis , Block Level , Cadence , power analysis , Chip Level

Dear Candidates We have a Immediate requirement of SAP UI5 & Fiori requirement for one of our Client at Bangalore Location. Summary Location: Bangalore Experience: 5+years experience level is required. Position:SAP UI5 & Fiori Immediate joiners p

Skills : OPA5 , Written Communication , impact assessment , UAT signoff , Sap Ui5 , Sap Fiori , Test Scripts

Job Description : 1. DFT 2. Synthesis 3. Place & Route - RTL2GDSII 4. SYN/STA 5. SignOff

Responsibilities: As a part of the Customer Solutions Signoff Team you will be mainly working with R&D, field sales/support organization and key customers on newly developed features and product engagements. The main tasks will be handling customer e

Skills : Applications Engineer , Sta , Spice Simulation , ASIC design flow , Vlsi Design , UNIX

Job Description : Roles & responsibilities 1. Gather requirements by having workshops, meetings and knowledge sharing sessions with the customer 2. Securing signoff on requirements from all stakeholders 3. Has an good knowledge of Peoplesoft FSCM mo

Skills : Assoc Prin Arch - Applications

Job Description : Roles & responsibilities 1. Gather requirements by having workshops, meetings and knowledge sharing sessions with the customer 2. Securing signoff on requirements from all stakeholders 3. Has an good knowledge of Peoplesoft FSCM mo

Skills : Assoc Prin Arch - Applications

Job Description : Job Description Responsible for schedule and quality goals Drive and define FCT signoff criteria setup flow methodology constraints definition. Drive TR to achieve best convergence methodology flow . Additional skills include Hands

Skills : SOC Design Engineer

Job Description : Job Description Responsible for schedule and quality goals Drive and define FCT signoff criteria setup flow methodology constraints definition Drive TR to achieve best convergence methodology flow Additional skills include HandsOn

Skills : SOC Design Engineer

Job Description : Job Description Responsible for schedule & quality goals. Drive & define FCT signoff criteria, setup, flow/methodology, constraints definition & validation, ACIO spec definition & validation & Syn & SD Caliber. Drive TR to achieve

Skills : SoC Full-Chip Timing Lead

Job Description : At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You will work with an elite team of physical design implementation engineers and have personal design responsibility, inc

Job Description : At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We offer amazing opportunities to grow, no matter where you are in your career. This opportunity is for a Product Enginee

We are now looking for an ASIC Design Engineer - Hardware. As a member of our ASIC backend/timing team, you'll be working on product designs, focusing on such tasks as clocks, timing convergence, chip layout planning, design optimizationandautomation

Job Description Roles and Responsibilities Hi, Greetings From Futures and Careers..!! Immediate requirement for Physical Design Engineer position . Designation : Design Engineer Experience: 4-10 years in setting up and run synthesis and P&R flow

Skills : Synthesis , PPA , Sta , power optimisation