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Physical Design Runset Development Manager

Sign On Solutions Private Limited
Bengaluru / Bangalore
12-20 years
Not Specified

12-15 years of experience is required in the physical design/ verification is required. Strong experience in developing the physical rule runsets in ICV/Calibre

Skills :

PDK Runset Dev.

Intel
Bengaluru / Bangalore
5-8 years
Not Specified

Job Description : Job Description Developing Physical design runsets for Intel process technologies is the primary job function. Working closely with the technology development teams in LTD (Logic Technology Division) to define and implement the tec

Physical Design Runset Development Manager

Intel
Bengaluru / Bangalore
12-15 years
Not Specified

Job Description : Job Description Developing Physical design runsets for Intel process technologies is the primary job function. Working closely with the technology development teams in LTD (Logic Technology Division) to define and implement the tec

Runset Developer

Intel
Bengaluru / Bangalore
6-8 years
Not Specified

Job Description : Job Description Developing the Physical design runsets for Intel process technologies is the primary job functions. Understanding the Design reference manuals, developing the specs, aligning with REB book content owners is the core

Runset Developer

Intel
Bengaluru / Bangalore
4-5 years
Not Specified

Job Description : Job Description Developing the Physical design runsets for Intel process technologies is the primary job functions. Understanding the Design reference manuals, developing the specs, aligning with REB book content owners is the core

Runset Developer

Intel
Bengaluru / Bangalore
4-5 years
Not Specified

Job Description : Job Description Developing the Physical design runsets for Intel process technologies is the primary job functions. Understanding the Design reference manuals, developing the specs, aligning with REB book content owners is the core

CAD Engineer

Intel
Bengaluru / Bangalore India
Not Specified

Job Description : Job Description Candidate develops and applies CAD engineering methods and techniques in the investigation and solution of technical problems in LV and DFM. You will be working on physical sign off tools, flow and methodologies.

Runset QA Engineer

Intel
Bengaluru / Bangalore
8-11 years
Not Specified

Job Description : Job Description In this role, candidate should be able to guide the work of 2-3 junior engineers. Physical Design Verification Runset Quality Checks is the primary job function. Debug the DRC/LVS rule deck failures during regressio

Software Engineer DP release lead

Intel
Bengaluru / Bangalore
5-7 years
Not Specified

Job Description : Job Description Technology Enablement Group (TEG) is a part of Platform Enablement Solutions Group (PESG). The charter of the group is to enable external foundry ecosystem to the product design teams across various domains.Person

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