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Responsibilities include RTL development, resolving system-level challenges, architecting, implementing, documenting and validating the memory controller IP cores.

Skills :

The successful candidate will be responsible for definition, design, verification and documentation for SOC development. The candidate will lead one or more design and verification teams in charge of development and implementation of complex network

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Lead engineer

Career Axes Engineering Services
Hyderabad / Secunderabad
8-13 years
Not Specified

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills :

Rtl Design Engineer

Angel And Genie
Bengaluru / Bangalore
3-5 years
Not Specified

Responsibilities include RTL development, resolving system-level challenges, architecting, implementing, documenting and validating the memory controller IP cores. <br> Familiar with different aspects of IP development: micro-architecture.

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Asic Verification Manager

Vitestork Consulting Private Limited
Hyderabad / Secunderabad
8-18 years
Not Specified

• Write verification specifications, verification plans, and documentation<br> • Develop test bench and automate regression plans<br> • Be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)<br>

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RTL Design Engineer

Tech Mahindra Limited
Bengaluru / Bangalore
3-8 years
Not Specified

Experience in IP design - DDR, USB, MIPI, PCIe, Serdes, SATA,

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Rtl Design Engineer

Sign On Solutions Private Limited
Bengaluru / Bangalore
3-6 years
Not Specified

A minimum of about 3 years’ experience in the area of Serial Protocols IPs or Subsystems. <br> • Design experience with any of high speed interfaces such as PCIe/USB/SATA is must

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Associate Project Manager

Career Axes Engineering Services
Hyderabad / Secunderabad
10-15 years
Not Specified

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

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Senior Rtl Design Engineer

Sign On Solutions Private Limited
Bengaluru / Bangalore
8-16 years
Not Specified

A minimum of about 8 years’ experience in the area of Serial Protocols IPs or Subsystems. <br> • Design experience with any of high speed interfaces such as PCIe/USB/SATA is must

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Physical Design Director/Lead

Global Technologies
Bengaluru / Bangalore
10-20 years
Not Specified

10-15 years- experience in chip implementation as a top-level lead.<br> Proven track record with multiple successful final production tape-outs at advanced finfet nodes preferably 7nm and below<br> Experience in all phases of the IC design process from RTL->

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PCIe Design Engineer

Sign On Solutions Private Limited
Bengaluru / Bangalore
4-10 years
Not Specified

• AXI3/4/5 experience is HIGHLY desired. <br> • PCIe Gen3/4/5 experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.

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Senior Verification engineer

Career Axes Engineering Services
Hyderabad / Secunderabad
5-8 years
Not Specified

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills :

Principal Engineer, Verification

Vitestork Consulting Private Limited
Hyderabad / Secunderabad
10-20 years
Not Specified

• Define and develop verification architecture and verification plan<br> • Define and develop verification methodologies<br> • Define and develop verification environments<br> • Write verification specifications, verification plans, and documentation<br>

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Senior STA & RTL Design Engineer

Mulya Consulting
Hyderabad / Secunderabad
5-10 years
Not Specified

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

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Principal STA Engineer

Mulya Consulting
Bengaluru / Bangalore
12-16 years
Not Specified

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

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Principal STA Engineer

Mulya Consulting
Hyderabad / Secunderabad
12-16 years
Not Specified

A minimum with 12-16 years of total experience in RTL

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Design Verification Engineer

Synergic Emergence
Bengaluru / Bangalore
12-20 years
Not Specified

10+ years of experience in Design Verification - Proven experience in Full Chip Verification from Test Plan Development<br> to tape-out sign-off.

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Principal STA Engineer

Mulya Consulting
Hyderabad / Secunderabad
12-16 years
Not Specified

A minimum with 12-16 years of total experience in RTL

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Sr. FPGA Engineer / Tech Lead - FPGA (URGENT )- BANGALORE

Hi Tides Consulting
Bengaluru / Bangalore
8-15 years
1200000 - 1300000 INR

Should have experience in VHDL/ Verilog programming for complex applications.<br> 2. Should have experience on Xilinx/ Microsemi/ Intel FPGA’s for aerospace or medical or<br> automotive domains.

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Engineering Manager - 3DXP Firmware Development

Mulya Consulting
Bengaluru / Bangalore
10-15 years
Not Specified

10+ years relevant working experience and 2+ years team management experience

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Emulation Manager

Mulya Consulting
Bengaluru / Bangalore
7-14 years
Not Specified

Looking for Emulation Manager

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Senior STA & RTL Design Engineer

Mulya Consulting
Hyderabad / Secunderabad
5-10 years
Not Specified

A Bachelor in Electrical Engineering or related discipline plus 5 years of experience

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Principal STA Engineer

Mulya Consulting
Hyderabad / Secunderabad
12-16 years
Not Specified

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

Skills :

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