rtl Jobs in India

Responsibilities include RTL development, resolving system-level challenges, architecting, implementing, documenting and validating the memory controller IP cores.

Skills : rtl development , micro-architecture , RTL , TB implementation , Synthesis , Lint , cdc , Rtl Design , Verilog , System Verilog , PERL , Python , Tcl

The successful candidate will be responsible for definition, design, verification and documentation for SOC development. The candidate will lead one or more design and verification teams in charge of development and implementation of complex network

Skills : ASIC , RTL , Verification Manager , Soc

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills : SV-OVM , RTL , AHB , Axi , Verification , RTL , Lead Engineer , System Verilog , Pci , Perl , Tcl , Verilog

Responsibilities include RTL development, resolving system-level challenges, architecting, implementing, documenting and validating the memory controller IP cores. <br> Familiar with different aspects of IP development: micro-architecture.

Skills : Rtl Design

• Write verification specifications, verification plans, and documentation<br> • Develop test bench and automate regression plans<br> • Be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)<br>

Skills : Asic verification , RTL , Soc , Verilog

Experience in IP design - DDR, USB, MIPI, PCIe, Serdes, SATA,

Skills : RTL Design Engineer , Rtl Design , RTL , MIPI , SERDES , Microcontrollers , DDR , Usb , Pcie , Sata

A minimum of about 3 years’ experience in the area of Serial Protocols IPs or Subsystems. <br> • Design experience with any of high speed interfaces such as PCIe/USB/SATA is must

Skills : Rtl Design , Axi , ASIC , Verilog , Pcie

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills : RAL , Uvm , Digital Verification , RTL , AHB , Axi , Associate Project Manager , System Verilog , Perl , Tcl , Usb , Ethernet

A minimum of about 8 years’ experience in the area of Serial Protocols IPs or Subsystems. <br> • Design experience with any of high speed interfaces such as PCIe/USB/SATA is must

Skills : Rtl Design , Axi , Verilog , Pcie , Sata , Networking

10-15 years- experience in chip implementation as a top-level lead.<br> Proven track record with multiple successful final production tape-outs at advanced finfet nodes preferably 7nm and below<br> Experience in all phases of the IC design process from RTL->

Skills : Physical Design , RTL , Chip Design , ASIC , VHDL , ASIC Design , SOC design , Soc , Verilog , Eda

• AXI3/4/5 experience is HIGHLY desired. <br> • PCIe Gen3/4/5 experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.

Skills : PCIe Design , RTL , Ip , Uvm , Axi

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills : Senior Verification engineer , Verification Engineer , SV-OVM , RTL , AHB , Axi , Architectural Design , Circuit Design , Physical Design , Verification , Fabrication , System Verilog , Perl , Tcl , Logic Design

• Define and develop verification architecture and verification plan<br> • Define and develop verification methodologies<br> • Define and develop verification environments<br> • Write verification specifications, verification plans, and documentation<br>

Skills : ASIC , Asic verification , RTL , VHDL , Soc , Verilog

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

Skills : Senior STA & RTL Design Engineer , STA Engineer , Rtl Design Engineer , DRAM

Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

Skills : RtL Design Verification Engineer , Rtl Design , Rtl Design Engineer , Verification CAD tools , NCSim , Design Compiler , Formality , primetime , Tcl , Perl

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

Skills : Principal STA Engineer , rtl development , full chip STA , EDA Tools , RTL Coding , Coding , Perl

A minimum with 12-16 years of total experience in RTL

Skills : Principal STA Engineer , rtl development , full chip STA , EDA Tools , RTL Coding , Coding , Perl

10+ years of experience in Design Verification - Proven experience in Full Chip Verification from Test Plan Development<br> to tape-out sign-off.

Skills : Debugging RTL in block and/or chip-level , IP block interoperability and SOC/System level , Uvm , Full Chip Verification. Writing System Verilog Assertions (SVAs). HW/SW Co-Verification NC Verilog , QuestaSim. , System Verilog , Vcs

A minimum with 12-16 years of total experience in RTL

Skills : Principal STA Engineer , rtl development , full chip STA , EDA Tools , RTL Coding , Coding , Perl

Should have experience in VHDL/ Verilog programming for complex applications.<br> 2. Should have experience on Xilinx/ Microsemi/ Intel FPGA’s for aerospace or medical or<br> automotive domains.

Skills : VHDL/ Verilog programming , Xilinx/ Microsemi/ Intel FPGA’s , RTL , Timing Analysis , Dsp

10+ years relevant working experience and 2+ years team management experience

Skills : 3DXP Firmware Development , RTL , , Fpga , Windows , Linux

Looking for Emulation Manager

Skills : emulation Manager , running system tests , rtl verification , Synopsys

A Bachelor in Electrical Engineering or related discipline plus 5 years of experience

Skills : RTL Design Engineer , EDA Tools , CAD , Modeling , Sta , RTL , Electrical Engineering

RTL Design, Implementation, Testing, Integration and delivery of FPGA based hardware systems for Defense applications.

Skills : FPGA Firmware Design , Rtl Design , Implementation , VHDL , FPGA code , XILINX Vivado , ALTERA Libero SoC , NanoXplore Xmap , Xpython , altera quartus , Testing , Scripting Language

A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience

Skills : Principal STA Engineer , rtl development , full chip STA , EDA Tools , RTL Coding , Coding , Perl