8-12 yrs of RTL Design and Development using VHDL/Verilog, FPGA Design Experience in development of modules related to RF Front End, DSP algorithms in MATLAB related to MIMO/Beamforming,Experience in LTE or any OFDM based PHY module development.
FGPA Design–RTL Design and Development using VHDL/Verilog. Experience in LTE or any OFDM based PHY module development. FPGA Design Experience in development of modules related to RF Front End (DDC/DUC/DPD/CFR).Work closely with RF board design
5+ years’ experience in physical implementation. Experience in all phases of the IC design process from RTL->GDS2 Physical implementation of SoC/Full-chip-level and/or high-speed CPU/GPU/DSP cores Experience in high-speed, low-power, mixed-signal So
10+years’ experience in chip implementation and 3-5 years as a technical lead/technical manager. Experience in all phases of the IC design process from RTL->GDS2 Physical implementation of SoC/Full-chip-leveland/or high-speed ARM/DSP/GPU cores Experi
The successful candidate will be responsible for definition, design, verification and documentation for SOC development. The candidate will lead one or more design and verification teams in charge of development and implementation of complex network
Responsibilities include RTL development, resolving system-level challenges, architecting, implementing, documenting and validating the memory controller IP cores. Familiar with different aspects of IP development: micro-architecture.
Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip