Work at various levels of implementation of hierarchical chip (Blocks and Top)
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Experience in Power Estimation, Power Grid Planning & Closure.<br> Experience in EM/IR Analysis and Signoff using Ansys Redhawk / Cadence Voltus tool<br> Block/Sub-system/SOC level IR Analysis (Static/Dynamic) and in-rush Analysis<br>
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Strong Experience in Physical Design & Physical Verification.<br> Working experience with tools like ICC2/ Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.<br> Proficiency using Perl,Tcl,Pytho<br> Exp:- 4Yrs to 12 Yrs, Location:- HYD/Bang/Pune
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Company: Qualcomm India Private LimitedJob Area: Engineering Group, Engineering Group > Hardware EngineeringJob Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilit
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Job Description Job Responsibilities: The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes. The employee is expected to take ownership of Full Ch
Relocation Level:Domestic Hiring Manager:SHRIKRISHNA PUNDOOR Recruiter:Ravi Tej M In this role as a PrincipalEngineer (Power Integrity) in Micron’s Non-Volatile Engineering Group, you will be responsible for crafting next generation products for Micr
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What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks
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Job Description : Job Description SoC Physical Design Lead: Lead PD execution of partitions/subsystems/SoC with full ownership from synthesis to TI. Must have experience on 10nm and below technology nodes. Responsible for schedule & quality goals.
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Company: Qualcomm India Private LimitedJob Area: Engineering Group, Engineering Group > Hardware EngineeringJob Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilit
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Job Description : Job Description Responsible for schedule & quality goals. Drive & define FCT signoff criteria, setup, flow/methodology, constraints definition & validation, ACIO spec definition & validation & Syn & SD Caliber. Drive TR to achieve
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