RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification. Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows.
In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal
They will be responsible for end to end Physical Design profile at our customer’s project(s) and should have prior experience in working on 10nm/7nm technology. In current set of projects they may have to work on 5nm/7nm technology
Under general supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design,Verification, Fabrication,Packaging of Chips
In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing.
Delivered with (as applicable) UVM, System Verilog, low power, SoC verification design flows, Functional & DFT Coverages Interfaced with designs/teams with embedded Analog design blocks Familiarity with Analog verification flows
Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip
Expertise in Floorplan , IO Placement , CTS and Routing .Timing closure support to maximize process node capability.Multi-voltage island-based floorplan design and support.Clock tree setup/debug and synthesis for optimal QoR.Die size estimation and b
• Knowledge of multiple Industry standard protocols –PCIe, NVMe, USB4.0, DDR, AXI, CHI, AHB, MIPI, Displayport, Ethernet • Knowledge of Clocking, Boot/Reset flows. • Experience with System Verilog/UVM SOC development environment is must