physical verification Jobs in Hyderabad

Under general supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design,Verification, Fabrication,Packaging of Chips

Skills : Physical Design Engineer , floorplanning , Power Grid Design , Placement , CTS , Sta , Power Integrity Analysis , Physical Verification , Chip finishing , Tk , Routing , Tcl , Perl

In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing.

Skills : Physical Design Engineer , floorplanning , Power Grid Design , Placement , CTS , Sta , Power Integrity Analysis , Physical Verification , Chip finishing , Tk , Routing , Tcl , Perl

In-depth knowledge and hands-on experience on Netlist2GDSII Implementation

Skills : Physical Design Technical Lead , floorplanning , Power Grid Design , Placement , CTS , Sta , Power Integrity Analysis , Physical Verification , Chip finishing , Tk , Routing , Tcl , Perl

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills : Senior Verification engineer , Verification Engineer , SV-OVM , RTL , AHB , Axi , Architectural Design , Circuit Design , Physical Design , Verification , Fabrication , System Verilog , Perl , Tcl , Logic Design

Strong Experience in Physical Design & Physical Verification.<br> Working experience with tools like ICC2/ Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.<br> Proficiency using Perl,Tcl,Pytho<br> Exp:- 4Yrs to 12 Yrs, Location:- HYD/Bang/Pune

Skills : Physical Design , Physical Verification , RTL2GDS , 16nm , 10nm , 7nm , Synthesis , Block Level , ICC2 , / Innovus , Primetime/Tempus , ICC2 , Synopsys

This position is a permanent position with our client (US Based Semiconductor Product Company with revenue more than 30 Billion USD)

Skills : Principal Engineer , Chip Lead , ASIC Chip Lead , Design , Verification , Dft , Physical Design , Fpga

Hands on experience in doing layout of High Speed Interface circuits like LVDS, HDMI, Display Port; PLLs, CDRs; ADCs, DACs; Regulators etc

Skills : LVDS , HDMI , Display Port , PLLs , CDRs , ADCs , DACs , Cadence Virtuoso , physical verification tools

This position is a permanent position with our client (US Based Semiconductor Product Company with revenue more than 30 Billion USD)

Skills : Principal Engineer , Chip Lead , ASIC Chip Lead , Design , Verification , Dft , Physical Design , Fpga

This position is a permanent position with our client (US Based Semiconductor Product Company with revenue more than 30 Billion USD)

Skills : Principal Engineer , Chip Lead , ASIC Chip Lead , Design , Verification , Dft , Physical Design , Fpga

This position is a permanent position with our client (US Based Semiconductor Product Company with revenue more than 30 Billion USD)

Skills : Principal Engineer , Chip Lead , ASIC Chip Lead , Design , Verification , Dft , Physical Design , Fpga

Strong System Verilog coding and debugging skills with in-depth knowledge of all the OOPs concepts<br> <br> 4-8 years of experience<br> <br> <br> <br>

Skills : System Verilog , Debugging , Oops Concepts

Experience in SOC Verification<br> <br> ·         Experience in UVM/SV based verification methodology is must<br> <br> ·         Candidates with CPU-Core, Peripherals, Low Power Verification or Modem domain are preferred.

Skills : SoC Verification

End to end IP verification lifecycle including coverage measurement

Skills : IP Verification

Looking for a Physical Algorithm Engineer for one of the reputed company in Hyderabad

Skills : Physical layer algorithm , Wireless

• Write verification specifications, verification plans, and documentation<br> • Develop test bench and automate regression plans<br> • Be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)<br>

Skills : Asic verification , RTL , Soc , Verilog

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills : SV-OVM , RTL , AHB , Axi , Verification , RTL , Lead Engineer , System Verilog , Pci , Perl , Tcl , Verilog

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chip

Skills : RAL , Uvm , Digital Verification , RTL , AHB , Axi , Associate Project Manager , System Verilog , Perl , Tcl , Usb , Ethernet

Excellent opportunity | Design Verification | PAN India

Skills : Design Verification Engineer , Design Verification , Verification Engineer , IP / Sub-system verification , SV/ UVM , system interface protocols , IP verification project cycle , Testbench Strategies , TB development , simulation debugging

• Define and develop verification architecture and verification plan<br> • Define and develop verification methodologies<br> • Define and develop verification environments<br> • Write verification specifications, verification plans, and documentation<br>

Skills : ASIC , Asic verification , RTL , VHDL , Soc , Verilog

Define and develop verification architecture<br> • Define and develop verification methodologies <br> • Define and develop verification environments <br> • Write verification specifications, verification plans, and documentation<br>

Skills : OVM/UVM , VHDL , System Verilog , Pci , Verilog

In this role as a DFT Technical Lead you will performs DFT implementation and verification activities of complex SoCs/ASICS by collaborating with cross functional teams and architects

Skills : DFT Technical Lead , full chip DFT design , vector generation , Verification , boundary scan , ATPG , ASIC Design , Jtag , Soc

Data Modeler <br> Hyderabad (Hi-tech City)<br> Full Time with Start-up Company<br> <br> Key Skills: SSIS, MS SQL Server, SSAS, Data Model, Physical Data Models, Data Element, dimensional modelling<br> <br> Minimum 8 years of experience with Data Modelling

Skills : Data Modeller , Physical Data Models , Data Element , dimensional modelling , SSIS , Ms Sql Server , Ssas , Data Model

Understand how all aspects of the SSD/Managed NAND work together including hardware, firmware, NAND, packaging, power, performance and reliability

Skills : Physical Design manager , physical design integration , ASIC Architect , Firmware Architect , NAND Media Architect , Firmware Development , System Architect

Hands-on technical ownership of SoC for top-down/bottom-up physical design integration

Skills : Principal Physical Design Engineer , Physical Design Engineer , physical design integration , EDA Tools , Tcl , Perl

Hands-on technical ownership of SoC for top-down/bottom-up physical design integration

Skills : Principal Physical Design Engineer , Physical Design Engineer , physical design integration , EDA Tools , Tcl , Perl