physical verification Jobs in Bengaluru bangalore

They will be responsible for end to end Physical Design profile at our customer’s project(s) and should have prior experience in working on 10nm/7nm technology. In current set of projects they may have to work on 5nm/7nm technology

Skills : Physical Design Lead , Physical Design Manager , Physical Design , Floor Planning , Placement , CTS , crosstalk avoidance , Physical Verification , routing

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal

Skills : Floor Planning , CTS , Sta , Physical Verification

Dear Candidate<br> <br> Greetings from Kiash Solutions!!!<br> <br> <br> <br> We have opportunity with one of the leading Semiconductor Organization. for Physical Design Engineer for Bangalore, Ahemadabad Location .Please find the jd for your reference. Kindly got through

Skills : Physical Design , Sta , Physical Design Engineer , Signoff , cts , Sta , Physical Verification

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.

Skills : floorplanning , CTS , Sta , Physical Verification

<br> Delivered with (as applicable) UVM, System Verilog, low power, SoC verification design flows, Functional & DFT Coverages<br> Interfaced with designs/teams with embedded Analog design blocks<br> Familiarity with Analog verification flows

Skills : Physical Verification , EDA flows&Methodologies , Soc verification design flows , ip delivery Digital design with VHDL , Verilog , System Verilog

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes

Skills : floorplanning , CTS , Sta , Physical Verification , Shell , Tcl , Perl , Python

VLSI Physical Verification - DRC-Vlsi Engineer : -Immediate Opening with our Top MNC Client Bangalore Location. <br>

Skills : VLSI Physical Verification - DRC-Vlsi Engineer

Strong Experience in Physical Design & Physical Verification.<br> Working experience with tools like ICC2/ Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.<br> Proficiency using Perl,Tcl,Pytho<br> Exp:- 4Yrs to 12 Yrs, Location:- HYD/Bang/Pune

Skills : Physical Design , Physical Verification , RTL2GDS , 16nm , 10nm , 7nm , Synthesis , Block Level , ICC2 , / Innovus , Primetime/Tempus , ICC2 , Synopsys

End to end IP verification lifecycle including coverage measurement

Skills : IP Verification

Verification/GLS<br> <br> <br> <br> <br> Job Description: DV engineer with good expertise in SV/UVM concepts.<br> <br> Understanding of DDR protocols preferred.<br> <br> Good debugging and communication skills.

Skills : GLS Verification

Experience in SOC Verification<br> <br> ·         Experience in UVM/SV based verification methodology is must<br> <br> ·         Candidates with CPU-Core, Peripherals, Low Power Verification or Modem domain are preferred.

Skills : SoC Verification

Experienced ASIC Verification engineer responsible for implementing and executing verification plan to verify DDR memory Controller/PHY features. <br> <br> Requires a strong background in digital verification from planning to coverage closure.

Skills : Asic verification

Minimum qualifications: * Bachelor's degree in Electrical Engineering or related field, or equivalent practical experience. * Experience with different physical verification checks like DRC, LVS, Antenna, ERC, PERC, ESD etc. * Experience in

The successful candidate will be responsible for definition, design, verification and documentation for SOC development. The candidate will lead one or more design and verification teams in charge of development and implementation of complex network

Skills : ASIC , RTL , Verification Manager , Soc

Job Description : Uses skills as a seasoned, experienced professional with a full understanding of industry practices and company policies and procedures; resolves a wide range of issues in imaginative as well as practical ways. This job is a fully

Skills : Senior Application Engineer - Physical Verification

SUb system verification, UVM, System verilog, 8-12years, Bangalore, Best in industry, Notice period max 30 days

Skills : SV UVM , verification strategy , testbench , SUb system verification , Uvm , Perl , Python , Scripting , System Verilog

We are looking out for a Formal verification Lead for one of the renowned IT firms

Skills : Formal Verification Lead

We are looking for Physical Design Lead/Manager with 8 to 15 years of experience on:<br> <br> · They will be responsible for end to end Physical Design profile at our customer’s project(s) and should have prior experience in working on 10nm/7nm technology.

Skills : Physical Design

10+ years of experience in Design Verification - Proven experience in Full Chip Verification from Test Plan Development<br> to tape-out sign-off.

Skills : Debugging RTL in block and/or chip-level , IP block interoperability and SOC/System level , Uvm , Full Chip Verification. Writing System Verilog Assertions (SVAs). HW/SW Co-Verification NC Verilog , QuestaSim. , System Verilog , Vcs

Floor planning/Power planning and Place and Route at block level and chip level,Clock Tree Synthesis, timing ecos and timing closure related PD activities,Integration of IO/Analog and Digital blocks,STA,TCL,PERLor PHYTON, physical verificationchecks

Skills : Principal / Staff Physical Design Engineer - synthesisplacementrtl to gds"place & route"pnrsta"timing closure""timing analysis"netlistgdsfloorplaning"floor planing""ir drop"chiproute

Should have 4 yrs to 10 yrs experience

Skills : SV UVM , Sub-system verification , Uvm , System Verilog

Company: Qualcomm India Private LimitedJob Area: Engineering Group, Engineering Group > Hardware EngineeringJob Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilit

Skills : Physical verification engineer

Job Description : Roles & Responsibilities: * Help grow customer satisfaction with Mentor’s PV tools. * Work with customers with varying design styles and methodologies to architect the most effective technical solutions. * Should be able t

Skills : Application Engineer (AE) - Physical Verification

Verification,ARM architecture, AHB,APB,AXI,3-5 years, Bangalore, upto 15 LPA<br>

Skills : Verification , arm architecture , AHB , APB , Axi , System Verilog

10-15 years- experience in chip implementation as a top-level lead.<br> Proven track record with multiple successful final production tape-outs at advanced finfet nodes preferably 7nm and below<br> Experience in all phases of the IC design process from RTL->

Skills : Physical Design , RTL , Chip Design , ASIC , VHDL , ASIC Design , SOC design , Soc , Verilog , Eda