physical design integration Jobs in Bangalore

Hands-on technical ownership of SoC for top-down/bottom-up physical design integration

Skills : Physical Design Engineer , physical design integration , STA analysis , IVD , EM analysis

10-15 years- experience in chip implementation as a top-level lead.<br> Proven track record with multiple successful final production tape-outs at advanced finfet nodes preferably 7nm and below<br> Experience in all phases of the IC design process from RTL->

Skills : Physical Design , RTL , Chip Design , ASIC , VHDL , ASIC Design , SOC design , Soc , Verilog , Eda

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills : floorplanning , block partitioning , Power planning , CTS

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal

Skills : Floor Planning , CTS , Sta , Physical Verification

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills : Floor Planning , Power planning , block partitioning

worked on hierarchical and block level STA analysis<br> <br> o good at debugging constraints and writing ECOs for timing fixes<br> <br> o must have worked on 10nm, 7nm, 5nm technology process nodes<br> <br> o should be familiar with DMSA or manual timing fixes

Skills : Static Timing Analysis

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.

Skills : floorplanning , CTS , Sta , Physical Verification

Notice Period: Max upto 20 days<br> <br> Work Location:<br> 23-56P, Devarabeesanahalli<br> Varthur Hobli, Outer Ring Road<br> Bengaluru<br> Karnataka<br> <br> Description:<br> <br> CW will assist the DE Leads in executing structural design (Physical Design) including Synthesis runs, P&R, A

Skills : ynopsys Design Compiler , ICCII , ICV , PrimeTime (for STA) , Synopsys Lynx Environment , Cadence INNOVUS , and scripting in TCL , PERL

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.

Skills : Sta , Physical Design , Floor Planning , Place & route , Eco

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes

Skills : floorplanning , CTS , Sta , Physical Verification , Shell , Tcl , Perl , Python

Expertise in ASIC design implementation flow and hierarchical physical design strategies, methodologies<br> <br>

Skills : Physical Design Engineer , ASIC Design , Dft , Tcl , Perl , Scripting

worked on lower technologies like 10nm, 7nm, 5nm process<br> <br> o Good knowledge in Resistance check, Static IR, Dynamic IR, power EM, Signal EM.<br> <br> o debugging skills are very important for the issues in EMIR<br> <br> o must have worked on Redhawk tool

Skills : redhawk , emir

4+ Years of Professional experience creating and maintaining component for PCB libraries.<br> Create Schematic Symbols from part specs and electrical Engineer’s request.<br> Create Physical footprints from part specs and design guidelines for IPC class 3 des

Skills : Pcb

RTL Design, Implementation, Testing, Integration and delivery of FPGA based hardware systems for Defense applications.

Skills : FPGA Firmware Design , Rtl Design , Implementation , VHDL , FPGA code , XILINX Vivado , ALTERA Libero SoC , NanoXplore Xmap , Xpython , altera quartus , Testing , Scripting Language

Work at various levels of implementation of hierarchical chip (Blocks and Top)

Skills : Senior Physical Design Engineer , Physical Design Engineer , Vlsi , EDA Tool , Innovus , Tempus , PrimeTime-SI , Voltus , redhawk , StarXT , Quantus , Calibre , LEC , python , Tcl

Programming languages - C, C++ , JAVA. Experience is Infotainment Testing<br> SCM - GIT, SVN, RTC, Clearcase

Skills : Operating system - Linux , Android(familiarity in posix standards) , Qnx

Looking for Physical Design/ Structural Design Engineers with scope of work encompassing synthesis, scan, floor planning, auto place and route, clock tree synthesis, equivalency verification, static timing analysis, reliability and layout closure.

Skills : Physical Design , Structural Design Engineers , RTL , ASIC integration , Vlsi , EDA Tools , Synopsys , CAD Tools , ASIC integration , Cadence , Mentor Graphic , Floor Planning tools , Perl , Python

looking for hardware design engineer<br> freshers can also apply

Skills : Hardware Design Engineer

C Programming and Linux Kernel & Linux Kernel Device Drivers. Design, develop, unit test, and document the Linux driver. Bring up the driver and unit test the driver features. Optimize the driver for maximum performance. Bug analysis/fixing

Skills : Linux Kernel Programming , Linux , C Programming , Networking , Kernel Programming , Kernel Configuration , Kernel Debugging , Kernel Device Drivers

Jenkins (Plugins) Job Creation , scheduling , Maintenance, Jenkins pipelining , Networking basics

Skills : Operating system - Linux , Android(familiarity in posix standards) , Sdlc , Qnx

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis.

Skills : ECO generation , ECO implemantation , power analysis

We are looking for talented individuals who are not just looking for a job, but for a fun career in a young startup that has a lot of potential and room to grow.

Skills : FULL STACK DEVELOPER , React J.s , Node J.s , Javascript , CSS , HTML

B.Tech in Electronics & Communication or Electrical engineering or equivalent with 5 to 10 years of relevant experience

Skills : Electronic design , Conceptual Design , Hardware Design , electronic circuits , Embedded , Product Design , VHDL coding , Timing Analysis , Fpga , Validation Testing

Location : Bangalore<br> <br> Experience : 4 to 10 years<br> <br> Notice period : Immediate to 30 days only

Skills : Java developer , Java Programmer , Java Engineer , microservice engineer , Lead Engineer , Lead Architect , Lead Consultant

Dear Candidate<br> <br> Greetings from Kiash Solutions!!!<br> <br> <br> <br> We have opportunity with one of the leading Semiconductor Organization. for Physical Design Engineer for Bangalore, Ahemadabad Location .Please find the jd for your reference. Kindly got through

Skills : Physical Design , Sta , Physical Design Engineer , Signoff , cts , Sta , Physical Verification