• Knowledge of multiple Industry standard protocols –PCIe, NVMe, USB4.0, DDR, AXI, CHI, AHB, MIPI, Displayport, Ethernet • Knowledge of Clocking, Boot/Reset flows. • Experience with System Verilog/UVM SOC development environment is must
• 5-9 years functional verification experience in complex IP/SubSystem/SoCs in RTL and Gate level. • Hands on experience using an industry standard verification methodology (UVM/VMM). • Hands on experience on System Verilog •
• BS/MS in EE, CE, or CS with 5 - 10 Yrs of experience in Verification. • Experience in specifying and developing the verification infrastructure for verifying video based designs. • Strong analytical problem solving, and attention to details.
• Write verification specifications, verification plans, and documentation • Develop test bench and automate regression plans • Be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)
• Define and develop verification architecture and verification plan • Define and develop verification methodologies • Define and develop verification environments • Write verification specifications, verification plans, and documentation
6 Years+ Technical development & delivery. Responsible for providing expertise in the software development life cycle, from concept, architecture, design, implementation, & testing. Leading & mentoring small-sized team.Architecture documents.