Delivered with (as applicable) UVM, System Verilog, low power, SoC verification design flows, Functional & DFT Coverages Interfaced with designs/teams with embedded Analog design blocks Familiarity with Analog verification flows
Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
Responsibilities: • Review System requirements as per Standards • Design Test Plans based on System requirements. • Design and develop code in Python (Robot Framework) • Develop automation for new features and fix bugs in existing feature automation.
Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification. Delivery of fully verified – including both functionally and test coverage.
Demonstrated track record in 5-10 years of project/program management experience in end-to-end IT Infrastructure Transformation/Migration/Upgrade/Implementation projects and IT Operations Transition projects
Selligence Solutions invites application for Technology Leadership role in Telecom Industry with an extensive knowledge in Telecom domain and one who has handled global operation in BSS/OSS domain. Extensive experience in Technology.