Experienced in various aspects of DFT - SCAN insertion, ATPG & JTAG, BSCAN. Test generation, coverage improvement, post-silicon debug.
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Looking for Physical Design/ Structural Design Engineers with scope of work encompassing synthesis, scan, floor planning, auto place and route, clock tree synthesis, equivalency verification, static timing analysis, reliability and layout closure.
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Bachelors or Masters degree in Electrical, Electronics with 5 to 10 years of relevant industry experience
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Experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC
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