icc2 Jobs in Bangalore

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal

Skills : Floor Planning , CTS , Sta , Physical Verification

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.

Skills : floorplanning , CTS , Sta , Physical Verification

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes

Skills : floorplanning , CTS , Sta , Physical Verification , Shell , Tcl , Perl , Python

Dear Candidate<br> <br> Greetings from Kiash Solutions!!!<br> <br> <br> <br> We have opportunity with one of the leading Semiconductor Organization. for Physical Design Engineer for Bangalore, Ahemadabad Location .Please find the jd for your reference. Kindly got through

Skills : Physical Design , Sta , Physical Design Engineer , Signoff , cts , Sta , Physical Verification

Floor planning/Power planning and Place and Route at block level and chip level Expert user of Synopsys ICC (or ICC2)

Skills : Physical Design , PNR ( Place and Route ) , ICC , Sta , Synthesis

Strong Experience in Physical Design & Physical Verification.<br> Working experience with tools like ICC2/ Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.<br> Proficiency using Perl,Tcl,Pytho<br> Exp:- 4Yrs to 12 Yrs, Location:- HYD/Bang/Pune

Skills : Physical Design , Physical Verification , RTL2GDS , 16nm , 10nm , 7nm , Synthesis , Block Level , ICC2 , / Innovus , Primetime/Tempus , ICC2 , Synopsys

Experience in Power Estimation, Power Grid Planning & Closure.<br> Experience in EM/IR Analysis and Signoff using Ansys Redhawk / Cadence Voltus tool<br> Block/Sub-system/SOC level IR Analysis (Static/Dynamic) and in-rush Analysis<br>

Skills : Power Design

Job Description : Job Description This position is for individual contributor role of enabling/deploying flow and methodologies for place and route tools and timing analysis, for a team that focuses on enabling Intel technology R&D. In this position

Skills : Design automation engineer for APR/PNR and timing

Job Description : Job Description This position is for individual contributor role of enabling/deploying flow and methodologies for place and route tools and timing analysis, for a team that focuses on enabling Intel technology R&D. In this position

Skills : Design automation engineer for APR/PNR and timing

Job Description : Job Description In this position you will be part a world-class IP physical design team developing groundbreaking high-performance GFX targeting High-End Graphics, Gaming, Artificial Intelligence, Media processing, and other applic

Skills : Synthesis & PD methodology-implementation Lead

Job Description : Job Description Component Design Engineers are responsible for the design and development of electronic components. Responsibilities may include: the design of chip layout circuit design, circuit checking, device evaluation and cha

Skills : Component Design Engineer

Responsibilities: ThePhysical Design Specialist will be an expert in Physical Design methodologies and flows and will drive customer adoption and sales of SNPS physical design tools and services.The PDS will be responsible for supporting large multi-

SrI Serdes Physical Implementation EngineerDescription: In this role, you will be responsible for the Physical Implementation of high speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off, in c

Job Description : Job Description : Deliver industry standard parasitic extraction tools / flows and capabilities for Intel's Customers. Primary responsibility includes but not limited to enablement of PDK Custom and ASIC extraction flows/ methodolo

Skills : PDK Extraction QA Engineer

Job Description : Job Description In this role candidate will be leading static timing analysis tools/flow and methodology development/deployment, which involves developing methodologies to support new process nodes as well as design features. Role

Skills : CAD engineer for Timing analysis and sign off flow

SrI Serdes PhysicalImplementationEngineer Description: In this role, you will be responsible for the Physical Implementation of high speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off, in cl

SrI Serdes Physical Implementation EngineerDescription: In this role, you will be responsible for the Physical Implementation of high speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off, in c

Job Description : Job Description In this position, you will be responsible for managing and working on all aspects of physical design activities of Intel's SoCs in lower technology nodes. The candidate should be able to drive all aspects of physica

Skills : SOC Design Engineer Lead

Job Description : Job Description Develops and applies computer aided design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems. Assessing architecture and hardware limitation

Skills : CAD Engineer

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks

Skills : Sr. Manager Physical Design (80808)

Job Description : Job Description In this position you will be part of a world class Graphics IP design team responsible for design and development of the Graphics IP's as part of the Graphics Hardware & Throughput computing team. This is a great op

Skills : Structural Design Engineer-RLS

Job Description : Job Description Responsible for structural and physical design of complex IP and SoC (System on Chip) in Ethernet domain. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, design conve

Skills : SOC Design Engineer

Job Description : Job Description Responsible for structural and physical design of complex IP and SoC (System on Chip) in Ethernet domain. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, design conve

Skills : SOC Design Engineer