• 5-9 years functional verification experience in complex IP/SubSystem/SoCs in RTL and Gate level. • Hands on experience using an industry standard verification methodology (UVM/VMM). • Hands on experience on System Verilog •
produce specifications for, design, develop, manufacture and install new or modified mechanical components or systems. Mechanical engineers need to be technically minded, able to demonstrate numerical and scientific ability and have problem-solving.
Enforce compliance with coding guidelines using code reviews etc. Schedule work to meet completion dates & technical specifications. Ensure that the requirements are adequately defined & designs are fully documented. To handle tasks independently.
Able to do route selection study, location class study, pigging study, tie-in , feasibility study, design basis , independently able to develop pipeline deliverable s, scope of work, route selection report, definition report, material grade selection