Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.
In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal
Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.
• Candidate should possess excellent oral and written communication skills• Candidate with good customer service skills would be preferred• Candidate should have 0-5 year of experience in Customer Support Voice Process.•
They will be responsible for end to end Physical Design profile at our customer’s project(s) and should have prior experience in working on 10nm/7nm technology. In current set of projects they may have to work on 5nm/7nm technology
The Business Analyst will assist with the implementation and support of business information systems across multiple departments. You are expected to develop new models that underpin sound business decisions.
This position will support building and strengthening the brand and creating marketing programs that drive Member acquisition and retention. The position requires a positive attitude, passion for marketing, sense of urgency and attention to detail.
• Floor planning/Power planning and Place and Route at block level and chip level • Expert user of Synopsys ICC (or ICC2) – Floor-planning, Place & Route and Clock Tree Synthesis • In depth knowledge of CTS and customized clock implementations
Floor planning/Power planning and Place and Route at block level and chip level,Clock Tree Synthesis, timing ecos and timing closure related PD activities,Integration of IO/Analog and Digital blocks,STA,TCL,PERLor PHYTON, physical verificationchecks