eda tool Jobs in Bangalore

Work at various levels of implementation of hierarchical chip (Blocks and Top)

Skills : Senior Physical Design Engineer , Physical Design Engineer , Vlsi , EDA Tool , Innovus , Tempus , PrimeTime-SI , Voltus , redhawk , StarXT , Quantus , Calibre , LEC , python , Tcl

• Bachelor Degree in Engineering.<br> • Hands-on experience in defining and validating chip level as well as block leveling timing constraints.<br> • Well versed in setting up timing signoff flows<br>

Skills : Sta , ECO generation , , Static Timing Analysis

• Experience in Model Based Design using Simulink/State flow tool.<br> • Experienced in scaling of Simulink/Target link models.<br> • Exposure to Model In Loop (MIL), Software In Loop (SIL), Processor In Loop (PIL), Hardware In Loop (HIL).<br> • Proficient in Sc

Skills : Simulink , HIL , PIL , SIL , Target link models , powertrain , Matlab , C , Python

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal

Skills : Floor Planning , CTS , Sta , Physical Verification

Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level

Skills : Dft , Scan Insertion , MBIST and JTAG , ATPG , Pattern validation , TetraMAX OR Cadence

Press tool Maker & Surface Grinder

Skills : Surface Grinder , Press Tool Maker

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.

Skills : floorplanning , CTS , Sta , Physical Verification

In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes

Skills : floorplanning , CTS , Sta , Physical Verification , Shell , Tcl , Perl , Python

Job Description Through understanding of digital design, RTL coding and simulation. Involved in architectural and micro architecture design. Experienced in Lint, CDC, logic synthesis, formal verification and static timing analysis. Worked wi

Skills : Tech Staff Engineer - Design

Job Description Through understanding of digital design, RTL coding and simulation. Involved in architectural and micro architecture design. Experienced in Lint, CDC, logic synthesis, formal verification and static timing analysis. Worked wi

Skills : Tech Staff Engineer - Design

• Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification<br> • Delivery of fully verified – including both functionally and test coverage w

Skills : ASIC , Verification , Uvm , Soc , Verilog

looking for desktop support engineer<br> freshers can also apply

Skills : Desktop Support Engineer , Hardware Engineer , Desktop Engineer , Technical Support Engineer , It Service Desk , Laptop Support , It Help Desk

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills : Floor Planning , Power planning , block partitioning

Experience in Dedicated in MIL & SIL based testing for Unit and Integration Testing.<br> Experience in Automotive domain mandatory (Chassis, DAS, LAMP)<br> Experience in ISO 26262 Functional Safety Standards (ASIL B or C or D)

Skills : MIL , SIL , Matlab.Embedded c , Testing Tools

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re pow

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.

Skills : Sta , Physical Design , Floor Planning , Place & route , Eco

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills : floorplanning , block partitioning , Power planning , CTS

Micron’s vision is to transform how the world uses information to enrich life for all.​Join an inclusive team focused on one thing: using our expertise in the relentless pursuit of innovation for customers and partners. The solutions we create help m

Skills : Staff Engineer - ASIC Physical Design

CAST API

Skills : Cast Api

Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog. <br>

Skills : Sta , VHDL , Vlsi , Static Timing Analysis , Verilog

Work with multiple project teams internal and outsourced development partners responsible for all stages of quality assurance for complex products and platforms, including testing strategy, analysis, coding, results evaluation, and proposed correct

Skills : REST , Html5 , Json , Raid , Scsi , SAS , Sata

Job Description Job Title: CAD Engineer Junior Level Microchip is seeking a junior level engineer for the Bangalore office. Microchip is a worldwide company with many sites through the world. We offer new employees visibility, hands-on learning, and

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis.

Skills : ECO generation , ECO implemantation , power analysis

Incumbent will be responsible for Functioning with clients, technical teams for securing & executing concurrent objectives.

Skills : ASIC , Verification , Fpga , Soc , Verilog

Experience working of SV and UVM methodology and experience of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required

Skills : Uvm , MIPI , System Verilog , Ethernet , Pcie , Usb