• Knowledge of multiple Industry standard protocols –PCIe, NVMe, USB4.0, DDR, AXI, CHI, AHB, MIPI, Displayport, Ethernet • Knowledge of Clocking, Boot/Reset flows. • Experience with System Verilog/UVM SOC development environment is must
Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification. Delivery of fully verified – including both functionally and test coverage.
We are looking for a candidate whose primary focus will be in applying Natural Language Processing (NLP) AI techniques, doing machine learning, and building high-quality prediction systems to classify data.
Bachelors/Masters in Electronics or equivalent degree with 9+ years of experience * Sound knowledge of Scan Stitching, Scan Compression, MBIST & JTAG Techniques * Should have good post silicon DFT bring-up and debug experience
Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
The successful candidate will work to become familiar with SOC/FPGA product line and provide customer focus solutions, application designs and design services in the area of High Speed protocols and Video Imaging Solutions.
• Define and develop verification architecture and verification plan • Define and develop verification methodologies • Define and develop verification environments • Write verification specifications, verification plans, and documentation
Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.
Work with multiple project teams internal and outsourced development partners responsible for all stages of quality assurance for complex products and platforms, including testing strategy, analysis, coding, results evaluation, and proposed correct
The successful candidate will work to become familiar with SOC/FPGA product line of our company and provide customer focus solutions, application designs and design services in the area of High Speed protocols and Video Imaging Solutions.
As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge
Delivered with (as applicable) UVM, System Verilog, low power, SoC verification design flows, Functional & DFT Coverages Interfaced with designs/teams with embedded Analog design blocks Familiarity with Analog verification flows
Design and implement networking / EMS / NMS solutions with high optimization and performance Come up with proof of concepts for critical modules/new frameworks Establish high, mid and micro level plans and estimates for project teams.
Posted: 4 months ago
Get noticed by recruiters
Give your career a boost with Monster's resume services.