Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification. Delivery of fully verified – including both functionally and test coverage.
Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge
Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.
Work with multiple project teams internal and outsourced development partners responsible for all stages of quality assurance for complex products and platforms, including testing strategy, analysis, coding, results evaluation, and proposed correct
Delivered with (as applicable) UVM, System Verilog, low power, SoC verification design flows, Functional & DFT Coverages Interfaced with designs/teams with embedded Analog design blocks Familiarity with Analog verification flows
Design and implement networking / EMS / NMS solutions with high optimization and performance Come up with proof of concepts for critical modules/new frameworks Establish high, mid and micro level plans and estimates for project teams.
3–5-year experience in diagnostics (software written specifically to test new hardware) development. Bootloader development (Uboot) and hardware bringup experience Familiarity with telecom/networking chassis-based systems. Good knowledge of C program
1) DDR Verification 2) PCIe Verification Lead ( 10+ Years) 3) IP Verification Lead 4) SOC Verification Engineer with knowledge on Emulation 5) Low power verification with hands on experience on UPF 6) CPU Verification Engineers 7) Functional Verifica
The team is actively looking for a Senior Analog Engineer to design/architect high performance data converters and other mixed signal products which use data converters. Responsibility includes designing analog build blocks for an ADC.
• Will work extensively with standard lab equipment, including oscilloscopes, meters, power supplies, source measure units and various other instruments. • Develop and improve automated validation bench set ups, test fixtures and device test programs
• Skilled use of standard lab equipment, including oscilloscopes, meters, power supplies, source measure units and various other instruments. • Develop and improve automated validation bench set ups, test fixtures and device test programs to validate
The team is actively looking for a Senior Analog Engineer to design/architect high performance data converters and other mixed signal products which use data converters. Responsibility includes performing the high-level architectural.
• Floor planning/Power planning and Place and Route at block level and chip level • Expert user of Synopsys ICC (or ICC2) – Floor-planning, Place & Route and Clock Tree Synthesis • In depth knowledge of CTS and customized clock implementations
Posted: 15 days ago
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