RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification. Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows.
The successful candidate will be responsible for definition, design, verification and documentation for SOC development. The candidate will lead one or more design and verification teams in charge of development and implementation of complex network
Delivered with (as applicable) UVM, System Verilog, low power, SoC verification design flows, Functional & DFT Coverages Interfaced with designs/teams with embedded Analog design blocks Familiarity with Analog verification flows
They will be responsible for end to end Physical Design profile at our customer’s project(s) and should have prior experience in working on 10nm/7nm technology. In current set of projects they may have to work on 5nm/7nm technology