FPGA Design Engineer:
· Expertise in understanding, gathering and finalizing the requirements for FPGA design.
· Should have worked on architecture into micro-architecture/detailed design
· Competent in basic digital design concepts, interfacing,
Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.
In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal
Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.
Posted: a month ago
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