Develop grammars definitions • Develop and unit test parsers for various languages • Map parsing trees into new representations • Develop analytics based on existing parse trees Design software structures, modules and design patterns.
FGPA Design–RTL Design and Development using VHDL/Verilog. Experience in LTE or any OFDM based PHY module development. FPGA Design Experience in development of modules related to RF Front End (DDC/DUC/DPD/CFR).Work closely with RF board design
FPGA Design Engineer:
· Expertise in understanding, gathering and finalizing the requirements for FPGA design.
· Should have worked on architecture into micro-architecture/detailed design
· Competent in basic digital design concepts, interfacing,
• Floor planning/Power planning and Place and Route at block level and chip level • Expert user of Synopsys ICC (or ICC2) – Floor-planning, Place & Route and Clock Tree Synthesis • In depth knowledge of CTS and customized clock implementations
The team is actively looking for a Senior Analog Engineer to design/architect high performance data converters and other mixed signal products which use data converters. Responsibility includes designing analog build blocks for an ADC.
8-12 yrs of RTL Design and Development using VHDL/Verilog, FPGA Design Experience in development of modules related to RF Front End, DSP algorithms in MATLAB related to MIMO/Beamforming,Experience in LTE or any OFDM based PHY module development.
RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification. Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows.