Must be strong in React and Node. Must have strong education. must be a hands on developer on both front end and backend . Must have strong experience in product development and keen in working early stage company(10 years old)
As a Principal Engineer, you will lead the full-stack development of one of Soroco’s major products by working cross-functionally with the product and design organizations. Within the product engineering team, this role reports dire
Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
10+years’ experience in chip implementation and 3-5 years as a technical lead/technical manager. Experience in all phases of the IC design process from RTL->GDS2 Physical implementation of SoC/Full-chip-leveland/or high-speed ARM/DSP/GPU cores Experi
• Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification • Delivery of fully verified – including both functionally and test coverage w
• Responsible for the Overall performance of the centre . • Responsible for the Continuous Improvement of the centre. • Responsible to maintain all the infrastructure. • To be Incharge of the 5 S activities
produce specifications for, design, develop, manufacture and install new or modified mechanical components or systems. Mechanical engineers need to be technically minded, able to demonstrate numerical and scientific ability and have problem-solving.
Hiring For Principal Engineer- Java Location- Mumbai/Bangalore Skills- Core java,Java,RDBMS,NOSQL,AWS tech,Message Queue Team Management Experience Mandate Work from home till june Telephonic rounds of interviews
Requirements: The candidates must be acquainted with the Administrative posts like Controller of Examination, Dean Student Welfare, Registrar functions, NAAC, IQAC, NIRF procedures and functioning, etc.
Floor planning/Power planning and Place and Route at block level and chip level,Clock Tree Synthesis, timing ecos and timing closure related PD activities,Integration of IO/Analog and Digital blocks,STA,TCL,PERLor PHYTON, physical verificationchecks
Posted: 2 months ago
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