• Define and develop verification architecture and verification plan • Define and develop verification methodologies • Define and develop verification environments • Write verification specifications, verification plans, and documentation
• Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification • Delivery of fully verified – including both functionally and test coverage w
• Write verification specifications, verification plans, and documentation • Develop test bench and automate regression plans • Be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)
10+years’ experience in chip implementation and 3-5 years as a technical lead/technical manager. Experience in all phases of the IC design process from RTL->GDS2 Physical implementation of SoC/Full-chip-leveland/or high-speed ARM/DSP/GPU cores Experi
The successful candidate will be responsible for definition, design, verification and documentation for SOC development. The candidate will lead one or more design and verification teams in charge of development and implementation of complex network
Under general supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design,Verification, Fabrication,Packaging of Chips
Backend Design Engineers Exp in High Speed, ASIC , CPU , GPU. Mentor graphics VS 2.6 and beyond , packaging experience ( 1st Priority) Packaging in Allegro (2nd Preference) Board designers with HDI experience using mentor Graphics.