Looking for a candidate with experience and interest in both manual/functional and automated testing in an SDET capacity.<br> <br>
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Responsibilities include RTL development, resolving system-level challenges, architecting, implementing, documenting and validating the memory controller IP cores. <br> Familiar with different aspects of IP development: micro-architecture.
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looking for desktop support engineer<br> freshers can also apply
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worked on hierarchical and block level STA analysis<br> <br> o good at debugging constraints and writing ECOs for timing fixes<br> <br> o must have worked on 10nm, 7nm, 5nm technology process nodes<br> <br> o should be familiar with DMSA or manual timing fixes
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Urgent requirement for Embedded Software Engineer for Bangalore location
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Have 2+ years of experience in AEM development, must have hands on experience
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worked on lower technologies like 10nm, 7nm, 5nm process<br> <br> o Good knowledge in Resistance check, Static IR, Dynamic IR, power EM, Signal EM.<br> <br> o debugging skills are very important for the issues in EMIR<br> <br> o must have worked on Redhawk tool
Lead Embedded Hardware Engineer you will be responsible for development of our products. These could include IOT devices, Control systems, Motherboards for different SOMs etc.
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In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes. Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Cal
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Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.
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• Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification<br> • Delivery of fully verified – including both functionally and test coverage w
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Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.
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Experience working of SV and UVM methodology and experience of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required
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Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level
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Incumbent will be responsible for Functioning with clients, technical teams for securing & executing concurrent objectives.
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In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.
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In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes
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Looking for the position of Senior Technical Lead - PCB Design And Embedded Systems: Require Candidates with 10+yrs of experience in PCB Design And Embedded Systems
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Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.
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Proven experience in constraints (Func/Test) handling, block and top level static timing analysis.
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• Experience in Model Based Design using Simulink/State flow tool.<br> • Experienced in scaling of Simulink/Target link models.<br> • Exposure to Model In Loop (MIL), Software In Loop (SIL), Processor In Loop (PIL), Hardware In Loop (HIL).<br> • Proficient in Sc
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Work with multiple project teams internal and outsourced development partners responsible for all stages of quality assurance for complex products and platforms, including testing strategy, analysis, coding, results evaluation, and proposed correct
Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog. <br>
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Data Entry
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• Bachelor Degree in Engineering.<br> • Hands-on experience in defining and validating chip level as well as block leveling timing constraints.<br> • Well versed in setting up timing signoff flows<br>
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Looking for the position of Power Electronics Engineer: Require Candidates with 6-8yrs of experience in Power Electronics
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Urgent Requirement for <br> Embedded Linux Device Driver<br> • Primary: Embedded C / C++ and Linux <br> • Linux Device Programming
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