Strong Experience in Physical Design & Physical Verification.<br> Working experience with tools like ICC2/ Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.<br> Proficiency using Perl,Tcl,Pytho<br> Exp:- 4Yrs to 12 Yrs, Location:- HYD/Bang/Pune
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Hands on experience in doing layout of High Speed Interface circuits like LVDS, HDMI, Display Port; PLLs, CDRs; ADCs, DACs; Regulators etc
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Looking for Principal DFT Engineer
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Cyient is a global engineering and technology solutions company. As a Design, Build, and Maintain partner for leading organizations worldwide, we take solution ownership across the value chain to help clients focus on their core, innovate, and stay a
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Req. ID: 231001Responsibilities include, but not limited to: * Hands-on write constraints for designs with complex clock structures * Constraint& mode reduction, own design timing across functions * Drive Design margins * Setup distribute
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Job Description : Responsibilities include, but not limited to: * Hands-on write constraints for designs with complex clock structures * Constraint& mode reduction, own design timing across functions * Drive Design margins * Setup distrib
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Job Description Job Responsibilities: The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes. The employee is expected to take ownership of Full Ch
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Job Description : Cyient is a global engineering and technology solutions company.As a Design, Build, and Maintain partner for leading organizations worldwide, we take solution ownership across the value chain to help clients focus on their core, in
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Job Description The Mixed Signal Development Group is responsible for delivering analog and mixed-signal IP to divisions within Microchip. We work with leading edge CMOS processes to produce analog integrated circuits for wireline and RF applicatio
Job Description The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes. The employee is expected to take ownership of Full Chip/multiple complex de
Job Description The Mixed Signal Development Group is responsible for delivering analog and mixed-signal IP to divisions within Microchip. We work with leading edge CMOS processes to produce analog integrated circuits for wireline and RF applicatio
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Job Description Job Responsibilities: The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes. The employee is expected to take ownership of Full Ch
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Job Description Job Responsibilities: The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes. The employee is expected to take ownership of Full Ch
We are now looking for a Layout Design Engineer! What you'll be doing: * Layout design involving memory arrays like multi-port register files, RAMs, and/or caches in advanced technologies. * Develop layouts for full custom memory desi
Job Description Job Responsibilities: The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes. The employee is expected to take ownership of Full Ch
NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, N
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Job Description Job Responsibilities: The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes. The employee is expected to take ownership of Full Ch
Job Description : 6+ years of hands on experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence E
Req. ID: 219005 As an experienced DFT engineer at Micron Technology, Inc., you will be involved with DFT implementation of SoCs. Successful Candidate will be responsible for architecture/implementation of DFT for zero DPPM GHz SoCs in sub-16nm techno
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Job Description : At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description for R&D Solutions Role: The Physical Verification R&D Solutions Software Engineering role is a multi-face