16nm Jobs in Bangalore

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills : floorplanning , block partitioning , Power planning , CTS

Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.

Skills : Floor Planning , Power planning , block partitioning

Work at various levels of implementation of hierarchical chip (Blocks and Top)

Skills : Senior Physical Design Engineer , Physical Design Engineer , Vlsi , EDA Tool , Innovus , Tempus , PrimeTime-SI , Voltus , redhawk , StarXT , Quantus , Calibre , LEC , python , Tcl

Strong Experience in Physical Design & Physical Verification.<br> Working experience with tools like ICC2/ Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.<br> Proficiency using Perl,Tcl,Pytho<br> Exp:- 4Yrs to 12 Yrs, Location:- HYD/Bang/Pune

Skills : Physical Design , Physical Verification , RTL2GDS , 16nm , 10nm , 7nm , Synthesis , Block Level , ICC2 , / Innovus , Primetime/Tempus , ICC2 , Synopsys

Looking for Principal DFT Engineer

Skills : Dft , Dft Engineer , Synopsys , Cadenc , Mentor Graphics Tools

Job Description Job Responsibilities: The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes. The employee is expected to take ownership of Full Ch

Job Description Job Responsibilities: The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes. The employee is expected to take ownership of Full Ch

Job Description : As an experienced DFT engineer at Micron Technology, Inc., you will be involved with DFT implementation of SoCs. Successful Candidate will be responsible for architecture/implementation of DFT for zero DPPM GHz SoCs in sub-16nm tec

Skills : Engineer , Electrical , Computer Science , Compliance , Engineering , Technology , Legal

Req. ID: 219005 As an experienced DFT engineer at Micron Technology, Inc., you will be involved with DFT implementation of SoCs. Successful Candidate will be responsible for architecture/implementation of DFT for zero DPPM GHz SoCs in sub-16nm techno

Skills : Principal Engineer I - ASIC DFT

Job Description The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes. The employee is expected to take ownership of Full Chip/multiple complex de

Skills : Principal Engineer - Physical Design

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks

Skills : Sr. Manager Physical Design (80808)

Job Description The Mixed Signal Development Group is responsible for delivering analog and mixed-signal IP to divisions within Microsemi. We work with leading edge CMOS processes to produce analog integrated circuits for wireline and RF application

NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, N

Skills : Senior Physical Design Engineer / Lead Physical Design Engineer