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  • Mulya Consulting
    Keyskills: Physical Design, Floor planning, Place & route, DRC, STA, Timing Closure, Timing Analysis, ECO, CTS, power planning, LVS, Netlist, floorplanning, power planning, GDSII, EDA, routing, IR drop, IP hardening, CPF, UPF
    Summary: Manager Physical Design - Bangalore
    Bengaluru / Bangalore
    10-15 years
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    Posted : 24th Dec 2018
  • Mulya Consulting
    Keyskills: MIPI, CSI, DSI, CPHY, DPHY, RTL, Verilog, ASIC, SOC, VHDL, Front End Design, Lint, CDC, DFT, LEC, UPF, Serdes
    Summary: Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers.experience in integration and validat..
    Bengaluru / Bangalore
    4-14 years
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    Posted : 7th Dec 2018
  • Mulya Consulting
    Keyskills: MAC, PTP, PCS, System Verilog, SV, Lint, CDC, DFT, LEC, UPF, ASIC, SoC, micro-architecture
    Summary: Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers.RTL Design and implementation of MAC/..
    Bengaluru / Bangalore
    4-14 years
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    Posted : 7th Dec 2018
  • Mulya Consulting
    Keyskills: RTL, Verilog, VHDL, SV, System Verilog, DSP, PCIE, Ethernet, Matlab, STA, Micro-Architecture, ASIC, SoC
    Summary: Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers.DSP fundamentals/Filter/FFT design/Da..
    Bengaluru / Bangalore
    4-14 years
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    Posted : 7th Dec 2018
  • Mulya Consulting
    Keyskills: Physical Design, P & R, STA, Synthesis, Netlist to GDSII implementation, SOC Design, ICC2, calibre, 40nm, 28nm, 16nm, 10nm
    Summary: Should have experience in Physical Design tasks on an SOC design, handled Netlist to GDS II implementation at Chip/partition level for atleast 2-3 designs.
    Bengaluru / Bangalore
    4-9 years
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    Posted : 25th Nov 2018
  • Mulya Consulting
    Keyskills: Physicla Design, Netlist to GDS II implementation, P & R, synthesis, STA, Calibre, ICC2, TCL, perl, Floor planning, 40nm, 28nm, 16nm, 10nm
    Summary: Hands on experience in Physical Design with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
    Bengaluru / Bangalore
    5-10 years
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    Posted : 25th Nov 2018
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