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  • Tech Mahindra Limited
    Keyskills: FPGA, ASIC RTL, RTL design... logic design, Verilog, SERDES... acceleration, packetizing modem data, e
    Summary: Domain (a): RTL design for digital signal processing logic design (in Verilog), like filter, fft, matrix operations, control, etc. Domain (b): FPGA, Ethernet packet processing (hardware accelerati..
    Bengaluru / Bangalore
    4-8 years
    Company Profile
    Posted : July 2018
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