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40 Job(s)
  • Keyskills: 16nm, 14nm, place and route, Physical Design, Timing Closure, block pnr, STA, SI analysys, EM...
    Summary: Proven ablity building a hierarchical, high performance processor in FINFET technology • Expert in developing flows to drive block PnR, Timing Closure and Final sign off. • ..
    Bengaluru / Bangalore
    10-20 years
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    Posted : August 2019
  • Keyskills: Physical Design, Full Chip PNR , Bump Placement, sub-micron designs , Floor Planning, Phys...
    Summary: Experienced in Full Chip PNR & Partitioning / Bump Placement
    Bengaluru / Bangalore
    5-12 years
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    Posted : 18th Oct 2019
  • Keyskills: Physical Design, Floor planning, DFT, Place & route, DRC, STA
    Summary: ChipEdge, one of Bangalore's leading and premium VLSI Training Institutes, is looking for Physical Design Engineers who are having passion for teaching, to deliver classroom training on weekd..
    Bengaluru / Bangalore
    7-12 years
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    Posted : 19th Sep 2019
  • Keyskills: ASIC, Physical Design, Clock Tree, Synthesis , Floor Planning, CAD Tool, P&R Flows
    Summary: Design with expertise in RTL-to-GDSII flow, floor planning, Clock tree synthesis and block-level/chip-level signoff Motivation to drive an exciting projectNeeds to be familiar with all aspects of ..
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    10-20 years
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    Posted : August 2019
  • Keyskills: Physical Design Engineer, ICC2/ Innovus, Perl, PNR, Floor planning, Synthesis/STA, Synopsys
    Summary: Urgent Opening for Sr. Physical Design Engineer for Bangalore, Noida, Hyderabad Exp- 5-8 yrs, CTC- 15 to 20 LPA, Mandatory Key Skills Required: ICC2/Innovus, Perl programming, Knowledge on PNR ..
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    5-8 years
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    Posted : 21st Oct 2019
  • Keyskills: Hardware Design, FPGA Design, RTL Design, Physical Design, Digital Design, ASIC Desig...
    Summary: • Responsible for the design & development of highly-sophisticated communication products for Cleint Solutions Infrastructure division.
    Malaysia
    4-14 years
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    Posted : August 2019
  • Keyskills: Verilog, System verilog, UVM, OVM, ASIC, SOC, VLSI, VHDL, Verification Engineer, MIMO, RTL, EDA, FPGA
    Summary: HI We have openings for ASIC/SOC/IP Verification Engineers for Bangalore , Hyderabad, Noida,Pune and Chennai I'm sharing the job description if you looking for job change pleas..
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    3-13 years
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    Posted : July 2019
  • Keyskills: Physical Design, Floor planning, Physical Verification, Timing Closure
    Summary: Looking the candidates who have experience in Semiconductor Industry.
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    4-10 years
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    Posted : 25th Oct 2019
  • Keyskills: Floor Planning, PNR, Physical Design
    Summary: Job Description : , Job Description , 1. Should have significant experience in Full chip floor planning, PnR & RDL Routing. , 2. Demonstrable experience in physical design implementation and conve..
    Hyderabad / Secunderabad
    7-12 years
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    Posted : 11th Nov 2019
  • Keyskills: ASIC, SoC, ASIC Architect, SoC Architect, STA, Verilog, SystemVerilog, PCIe, NVMe, DFT...
    Summary: exp with all aspects of the SOC design and implementation flow – including coverage driven verification, synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop – and an understandi..
    Hyderabad / Secunderabad
    15-25 years
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    Posted : 9th Nov 2019
  • Keyskills: ASIC, SoC, ASIC Architect, SoC Architect, STA, Verilog, SystemVerilog, PCIe, NVMe, DFT...
    Summary: exp with all aspects of the SOC design and implementation flow – including coverage driven verification, synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop – and an understandi..
    Hyderabad / Secunderabad
    10-20 years
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    Posted : 9th Nov 2019
  • Confidential
    Keyskills: Physical Design, Floor planning, Static Timing Analysis, closing time , RTL Design, Physical Verification
    Summary: Physical Design -VLSI Digital
    Bengaluru / Bangalore
    4-12 years
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    Posted : May 2019
  • Keyskills: Digital Design Engineer, Micro Architecture planning, SOC, , RTL Design, Integration plann...
    Summary: Looking for Senior / Digital Design Engineer.Experience of integrating embedded processor cores, industry standard IOs and mixed signal devices is required.
    Bengaluru / Bangalore
    5-9 years
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    Posted : July 2019
  • Keyskills: Netlist, GDSII, PD, Implementation flow, PnR, APR, RTL, Low power design, ASIC, VLSI, Floor pla...
    Summary: Floor planning, Power planning, Placement, CTS, Routing, Extraction, DFM
    Bengaluru / Bangalore
    2-8 years
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    Posted : August 2019
  • Keyskills: STA, Synthesis, DRC, PNR, Timing Closure, Placement, LVS, ICC, Routing, Physical Design
    Summary: Job Description: , * Contribute in developing the complete Netlist to GDS2 automation flow using PNR tools like ICC or Encounter in 16FF/10FF/7FF Technologies. , * Define the Floor Plan/placemen..
    Bengaluru / Bangalore
    5-10 years
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    Posted : 30th Sep 2019
  • Keyskills: Staff IC Design Engineer - Project Lead / Manager, Analog Design, Digital Design/Verifi...
    Summary: Job Description : , Staff IC Design Engineer - Project Lead / Manager This req is for a leading Semi-Conductor client for Chennai location. Responsibilities: Lead MCU-based Global SoC Project Team..
    Chennai
    8-13 years
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    Posted : 31st Oct 2019
  • Keyskills: Planning Engineer, Project Initiation, Design & Construction, Primavera, Primavera P6.
    Summary: LOOKING FOR PLANNING ENGINEER- THE PROFILE IS GIVEN FOR YOUR KIND REFERENCE.
    Hyderabad / Secunderabad
    5-10 years
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    Posted : June 2019
  • Keyskills: "ASIC", sta, mcmm, "PTSI", "Perl Scripting", "PCI"...
    Summary: Experienced in Synopsys d(Design compiler DC/DC-T/DC-G) Flow.
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    5-12 years
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    Posted : August 2019
  • Keyskills: "Physical Design", snps, "CDN", cts, "DRC", "LVS", "GDS"
    Summary: Experience in Physical Design implementation.
    Hyderabad / Secunderabad
    3-12 years
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    Posted : August 2019
  • Keyskills: Principal Engineer , RTL coding, Verilog, VHDL, System Verilog, RTL, Design tools, Mod...
    Summary: At least 8-year of strong experience in digital design and RTL coding (Verilog/VHDL/System Verilog)
    Hyderabad / Secunderabad
    8-12 years
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    Posted : 18th Sep 2019
  • Keyskills: ASIC, Verilog, VHDL, SOC, System verilog, VLSI, uvm
    Summary: we are actively looking for verification Engineers who are strong into Verilog/VHDL and UVM we have openings with Both services and Product companies in Bangalore/Hyderabad/Pune/Chennai
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    3-13 years
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    Posted : 12th Oct 2019
  • Keyskills: Soc, testplan, testbench, architecture, schedule, milestone planning, tracking & delive...
    Summary: SoC verification is a must. Experience in writing and debugging 'C' testcases for SoC verification is a must. Must have good debugging skills. ARM based SoC experience is a big plus. ..
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    3-13 years
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    Posted : 2nd Oct 2019
  • Keyskills: PGA design tools: Synplify, Vivado, XILINX ISE, Work experience in Xilinx FPGA based ...
    Summary: Experience : 4 to 8 years. Job Description: Hands on experience with FPGA design tools: Synplify, Vivado, XILINX ISE, Work experience in Xilinx FPGA based design implementation. FPGA RTL coding(V..
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    4-8 years
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    Posted : 6th Nov 2019
  • Keyskills: PCIE/Ethernet/USB protocols, NVME, UVM, Analog Verification, SoC verification, ASIC simul...
    Summary: PCIE/Ethernet/USB protocols,NVME sub-systems,developing UVM-based SV test-benches,defining block,sub-system & SOC top level test plans,ASIC simulation tools &advanced verification methods,debuggin..
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    4-14 years
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    Posted : 25th Oct 2019
  • Keyskills: Physical design, Synthesis, Static Timing Analysis, EM/IR, Noise Analysis, Implementati...
    Summary: BTech/MTech degree from reputed institutes (IIT, NIT or top universities) in Electrical/Electronics with 2-7 years of experience
    Bengaluru / Bangalore
    2-7 years
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    Posted : July 2019
  • Keyskills: Fresher , Graduate Trainee/Management Trainee , Chemical Engineer , Civil Engineer , Desi...
    Pune
    5-10 years
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    Posted : August 2019
  • Keyskills: PCI, Protocols, Ethernet, USB, nvme, SOC, uvm, SVT, PCIE, nvme, SOC, ASIC, uvm, System Verilog, soc test plan
    Summary: We have openings for Senior Design Verification Engineer with Senior PCIE / Ethernet/ USB Protocol at Hyderabad location
    Bengaluru / Bangalore
    4-9 years
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    Posted : September 2019
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