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40 Job(s)
  • Keyskills: Physical Design engineers, physical design, static timing analysis, STA, floorplanning, ...
    Summary: Job Description : , Requirements Must have experience with multiple successful tapeouts for 65nm and smaller geometries. The candidate needs to be self-motivated and an excellent team player, expe..
    Chennai
    8-15 years
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    Posted : 31st Oct 2019
  • Keyskills: Block/Chip physical design, Physical Design Engineer, Innovus/ICC2, Calibre, Primetime-SI...
    Summary: Responsibilities:  • Block/Chip physical design implementation and integration in finfet process • Design functional equivalence, timing/performance, xtalk checks • Physical Verification fo..
    Bengaluru / Bangalore
    6-10 years
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    Posted : August 2019
  • Keyskills: Physical Design Engineer, ICC2/ Innovus, Perl, PNR, Floor planning, Synthesis/STA, Synopsys
    Summary: Urgent Opening for Sr. Physical Design Engineer for Bangalore, Noida, Hyderabad Exp- 5-8 yrs, CTC- 15 to 20 LPA, Mandatory Key Skills Required: ICC2/Innovus, Perl programming, Knowledge on PNR ..
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    5-8 years
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    Posted : 21st Oct 2019
  • Keyskills: Design Engineer, RTL Integration , 32 bit microcontroller, RTL, regression simulations, ...
    Summary: Job Description : , Principal Design Engineer Description SoC level RTL Integration of 32 bit microcontroller product Technical support to the SoC team on integration and System level verification..
    Bengaluru / Bangalore
    6-10 years
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    Posted : 31st Oct 2019
  • Keyskills: RTL Design Engineer , RTL Design , DCT, DCG , Cadence RC, genus, multi-voltage, power aware...
    Summary: Knowledge in RTL design. (PLDRC/CDC,Synopsys Design Compiler Synthesis- DCT/DCG and/or Cadence RC/Genus). Hands on with multi-voltage, power aware synthesis, UPF flows-(LEC/ Synopsys VC formal- Pt..
    Bengaluru / Bangalore
    7-12 years
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    Posted : 8th Nov 2019
  • Keyskills: RTL frontend , design Engineer, Verilog, System Verilog RTL design , RTL synthesis, Design...
    Summary: Job Description : , RTL frontend design Engineer RTL frontend design Engineer 6 - 8 years experience in Verilog/System Verilog RTL design and verification RTL synthesis using Design compiler FPGA ..
    Chennai
    6-8 years
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    Posted : 31st Oct 2019
  • Confidential
    Keyskills: Physical Design, Floor planning, Static Timing Analysis, closing time , RTL Design, Physical Verification
    Summary: Physical Design -VLSI Digital
    Bengaluru / Bangalore
    4-12 years
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    Posted : May 2019
  • Keyskills: Memory Compiler, Memory Design, SRAM
    Summary: We are researching on Circuit Design Engineer who has good experience in Memory Complier Engineer with 4-7 years of experience.
    Bengaluru / Bangalore
    4-7 years
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    Posted : May 2019
  • Keyskills: Software Engineer, Software developer, Software programmer, Data Plane, 3GPP nodes, AMF, SM...
    Summary: Responsible for implementing new features/microservices for 5G core network nodes in cloud native environment.
    Bengaluru / Bangalore
    9-18 years
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    Posted : June 2019
  • Keyskills: Memory Design, Memory Compiler, Memory Design, SRAM
    Summary: We believe that the future of Chip making is knowing how they’ll perform before they’re designed & developed. Our client builds the products that power this revolution. we’re looking for passionat..
    Bengaluru / Bangalore
    2-5 years
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    Posted : June 2019
  • Keyskills: HFC DESIGNER, HFC networks, Node upgrades, HFC network designHFC network design , comput...
    Summary: Production of accurate, cost effective and efficient network design and / or drafting for the CATV industry. The job will also consist of checking the quality of production designs and helpin..
    Bengaluru / Bangalore
    5-10 years
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    Posted : June 2019
  • Keyskills: Digital Design Engineer, Micro Architecture planning, SOC, , RTL Design, Integration plann...
    Summary: Looking for Senior / Digital Design Engineer.Experience of integrating embedded processor cores, industry standard IOs and mixed signal devices is required.
    Bengaluru / Bangalore
    5-9 years
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    Posted : July 2019
  • Keyskills: Physical design, Synthesis, Static Timing Analysis, EM/IR, Noise Analysis, Implementati...
    Summary: BTech/MTech degree from reputed institutes (IIT, NIT or top universities) in Electrical/Electronics with 2-7 years of experience
    Bengaluru / Bangalore
    2-7 years
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    Posted : July 2019
  • Keyskills: RTL, RTL Engineer, RTL DESIGN, Verilog, RDMA, TCP, IP, UDP, NETWORKING, CSH, AWK, SED, PERL
    Summary: DESIGNATION: RTL ENGINEER ABOUT CLIENT: MNC (Name will be discussed during the telephonic discussion) WORK LOCATION: Bangalore - Bannerghatta Road
    Bengaluru / Bangalore
    5-12 years
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    Posted : June 2019
  • Keyskills: Physical Design, Physical Design Engineer, physical design tools, Physical Design Flow Tool, Route, CTS
    Summary: Expertise in Physical Design activities: Floor-planning, CTS, P&R, Extraction, Power IR/EM, Physical Verification (DRC/LVS) and Signal Integrity
    Bengaluru / Bangalore
    5-8 years
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    Posted : 18th Sep 2019
  • Keyskills: Senior Design Engineer, VLSI, RTL Design, Cadence Design
    Summary: 6 to 10 years of experience in VLSI / RTL design.Experienced in Lint, CDC, logic synthesis, formal verification and static timing analysis.
    Bengaluru / Bangalore
    6-10 years
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    Posted : 18th Sep 2019
  • Keyskills: STA, Synthesis, DRC, PNR, Timing Closure, Placement, LVS, ICC, Routing, Physical Design
    Summary: Job Description: , * Contribute in developing the complete Netlist to GDS2 automation flow using PNR tools like ICC or Encounter in 16FF/10FF/7FF Technologies. , * Define the Floor Plan/placemen..
    Bengaluru / Bangalore
    5-10 years
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    Posted : 30th Sep 2019
  • Keyskills: software validation Engineer, Validation Engineer, RTL design, FPGA , FPGA architecture...
    Summary: As a member of software validation team, you will play a key role in achieving Quartus software quality and functional validation.
    Bengaluru / Bangalore
    5-15 years
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    Posted : 21st Oct 2019
  • Keyskills: C ++, OO Design, SW abstraction , Python, Compiler design, ML kernels, Code Generation
    Summary: You will be working on cutting edge problems in Deep Learning for Internal Nervana SW Stack
    Bengaluru / Bangalore
    5-15 years
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    Posted : 21st Oct 2019
  • Keyskills: Physical Design Engineer, embedded , Embedded Software, Programming, Microsoft Technologi...
    Summary: As part of the Ampere Computing Physical Design team, you will be working on cutting-edge designs in 7nm and 16nm process nodes. You will be responsible for and own all aspects of physical design ..
    Bengaluru / Bangalore, Hyderabad / Secunderabad
    0-5 years
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    Posted : 23rd Oct 2019
  • Keyskills: Staff Engineer - Physical Design, Physical Design Engineer, EM, IR analysis, Verficat...
    Summary: 10+ years of experience running an industry standard EDA tool for fullchip assembly and Physical Verification(LVS/DRC) is require
    Bengaluru / Bangalore
    10-15 years
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    Posted : 30th Oct 2019
  • Keyskills: Graphic Designer, Graphic Design, Photoshop, Illustrator, Indesign, Graphic Designing, Phot...
    Summary: Hiring for graphic designing profile. experience. : MIN. 1yr. Salary : 2.4Lpa. working : 5 & a half days working call SUMITA 9953635353 & email [HIDDEN TEXT].
    Gurgaon / Gurugram
    1-2 years
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    Posted : July 2019
  • Keyskills: ASIC Physical Design Engineer, ASIC, ASIC Design, Application-specific integrated circui...
    Summary: Floor-planning, Timing constraints, Physical synthesis, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
    Noida
    5-10 years
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    Posted : July 2019
  • Keyskills: Do-254, FPGA Design, VHDL, FPGA, RTL, Design Engineer, Web designer, Dreamweaver
    Summary: We are looking for very smart candidates for our customer on going requirement where chance for onside sweden as well hurry up we have limited vacancy.
    Hyderabad / Secunderabad
    4-6 years
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    Posted : July 2019
  • Keyskills: Physical Design, Floor planning, DFT, LVS, Place & route, DRC, STA, Backend design, RTL Desig...
    Summary: Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the de..
    Hyderabad / Secunderabad
    15-22 years
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    Posted : August 2019
  • Keyskills: Packet Core Engineer, Mobile Packet Core, SGSN, GGSN, LTE ASR 5, Alarm Monitoring, test...
    Summary: Hiring packet core Engineers for L1
    Bhuj, Palanpur
    2-4 years
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    Posted : August 2019
  • Keyskills: Principal Engineer , RTL coding, Verilog, VHDL, System Verilog, RTL, Design tools, Mod...
    Summary: At least 8-year of strong experience in digital design and RTL coding (Verilog/VHDL/System Verilog)
    Hyderabad / Secunderabad
    8-12 years
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    Posted : 18th Sep 2019
  • Keyskills: Emulation Engineer , Emulation, FPGA, RTL design, RTL, Verilog , C, C++, Perl, Python
    Summary: Creating Emulation/FPGA models from an RTL design using Emulation/FPGA synthesis, partitioning and routing tools.
    Hyderabad / Secunderabad
    5-10 years
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    Posted : 21st Oct 2019
  • Keyskills: Physical Design Engineer, embedded , Embedded Software, Programming, Microsoft Technologi...
    Summary: As part of the Ampere Computing Physical Design team, you will be working on cutting-edge designs in 7nm and 16nm process nodes. You will be responsible for and own all aspects of physical design ..
    Chennai, Mumbai
    0-5 years
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    Posted : 26th Oct 2019
  • Keyskills: SGSN, GGSN, MME, SGW, PGW, Packet Core, 4G, L2 Packet Core Engineer, Packet Core Engineer, Pa...
    Summary: Expertise in Packet Core elements like SGSN / GGSN / DNS / AAA / PCRF / ASR-5X / SGW / PGW / MME / Nexus Platform: VPC, VDC, VNF.
    Gurgaon / Gurugram, Mumbai
    3-8 years
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    Posted : 15th Oct 2019
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