Verification Engineer

Verification Engineer

5 - 10 Years
Not Specified

Job Description

Roles and Responsibilities :
Minimum 3 to 4 years of experience in System Verilog HVL.
Minimum 2 to 3 years of experience in UVM.
Hands on experience of developing assertion, checkers, coverage and scenario creation.
Must have executed at-least 2 SoC Verification project
Experience in developing test and coverage plan, Verification environment and validation plan.
Knowledge of atleast one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.
Expertise in IP as well as SOC verification
Perl/shell scripting is a good to have


TechnoGen, Inc. is an ISO 9001:2015, ISO 20000-1:2011, ISO 27001:2013 and CMMI Level 3 Global IT Services and Consulting Company headquartered in Chantilly, Virginia and Offshore Development Center in Hyderabad, India. TechnoGen, Inc. (TGI) is a Minority & Women-Owned Small Business with over 16 years of experience providing end to end IT Services and Solutions to the Public and Private sectors. TGI provides highly skilled and certied professionals and has successfully executed more than 345 projects. TechnoGen is committed to helping our clients solve complex problems and achieve their goals, on time and under budget.

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