Staff Engineer - Design Verification
Exp: 10-15 yrs.
Roles & Responsibility
- Architect and implement simulation test bench in UVM.
- Develop and execute test-plans for verifying correctness and performance of the design.
- Own and debug failures in simulation to root-cause problems
- Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations
• Strong background in Soc verification methodology and test bench development using HVL such as Verilog, System Verilog, UVM and C/C++.
• Strong verification skills, understanding of methodology (object-oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations).
• Knowledge of Unix/Linux environment and scripting (shell/Perl/Python) is a plus.
• Demonstrates good analysis and problem-solving skills.
• Must have the ability to multi-task in a fast-paced environment.
• Must have effective interpersonal and teamwork skills and excellent communication skills.
• Ability to interface internally and externally with all levels of the organization.
• Participate in problem solving and quality improvement activities.
• BS in CS/EE with 10+ years of relevant experience.