Staff Engineer, CAD

Staff Engineer, CAD

Hyderabad / Secunderabad
10 - 13 Years
Not Specified

Job Description


Job Description
Job Description: (Brief summary of position)
You will be part of the team that develops FPGA and FPGA SOC products, which will be used in leading electronic systems. You will be involved in setting up, maintaining, and debugging the Cadence full-custom environment. This includes making customizations to foundry PDK, writing new Cadence PCells, scripting (SKILL, Perl, Python), and customizing Cadence netlisting environment. You need to be familiar with Cadence Database organization and structure. You will participate in the architecture, organization, and development of new CAD flows. You will have an opportunity to learn, understand, and work with integration of Non-Volatile Memory (NVM) technology used in our FPGA and SOC architectures. You will work closely with silicon design engineers, technology development engineers, and foundries to understand construction of new devices.
Job Responsibilities: (Bullet point list of primary requirements)

  • In-depth experience with setting up Cadence full-custom design environment (in both Virtuoso 6 & 12).
  • Understanding of 14nm and below process technologies, including FinFet.
  • Experience with Pcell creation, debugging, and migration flows.
  • Work with CDL, hspiceD and Verilog netlisting customizations.
  • In-depth knowledge of Cadence VXL and assist layout engineers resolve VXL issues.
  • Experienced in SKILL/Perl/Python scripting for design automation.
  • Interface with cross-functional teams on various CAD requests.
  • Good communication skills a key requirement for coordinating tasks across all different sites in different time zones.
Job Requirements
Required Qualifications: (Education and related work experience)
  • BSEE or MSEE and 10+ years of relevant work experience.
  • In-depth experience with setting up Cadence full-custom design environment (in both Virtuoso 6 & 12).
  • Understanding of 14nm and below process technologies, including FinFet.
  • Experience with Pcell creation, debugging, and migration flows.
  • Work with CDL, hspiceD and Verilog netlisting customizations.
  • In-depth knowledge of Cadence VXL and assist layout engineers resolve VXL issues.
  • Experienced in SKILL/Perl/Python scripting for design automation.
  • Interface with cross-functional teams on various CAD requests.
  • Good communication skills a key requirement for coordinating tasks across all different sites in different time zones.

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