SoC Design Engineer

SoC Design Engineer

Intel
14-17 years
Not Specified

Job Description


Job Description
Xeon Server Solution (XSS) group in Intel is responsible for delivering complex Servers SoC catering to high bandwidth memory requirements for Data- center and cloud applications.
This is a great opportunity to join a talented team and will include lots of product innovation on cutting edge process technologies. The selected candidate will be responsible for driving fullchip, subsystem physical design execution from Bangalore site. Activities will include, but not be limited to, full chip activities from FP, Synthesis, Design planning, analog integration/routes, PG grid, BUMP planning, RDL, Power Domain implementation, CTS, Routing and congestion resolution, Timing closure, Formal Verification and Power aware verification, Design Convergence, Timing and Reliability/Physical Signoff (EM, IR, DRC, Antenna and so on). Some of the selected candidates may also be involved at times in methodology development/customization for RTL2GDS construction and signoff flows.
Qualifications
Solid track record of taping out multiple chips on advanced process technology nodes such as 7nm, 10nm
Hands-on have experience on industry standard EDA tools such as Synopsys DC ICC2, Fusion Compiler and/or Cadence Innovus along with Synopsys PrimeTime, Mentor Calibre is mandatory.
Experience in all Physical Design Activities FP, Fulll Chip Layout, APR, Timing, Clocking, Power Delivery and Physical verification. Expertise in Design Planning, full chip layout activities and handling/managing all stakeholders.
Thorough technical understanding of backend challenges such as place and route on advanced process nodes, Static Timing Analysis for high frequency designs, formal equivalence check, low power design methodology and verification, etc are highly desired skills
Candidate should possess good communication skills to thrive in a multicultural environment and be capable of providing status updates to Sr Management
Should be able to manage ambiguity and schedule challenges. Must be a team player.
The selected candidate must have had prior leadership/management experience and should have demonstrated an ability to lead a team towards multiple project completions.
Candidates with experience in leading end-to-end physical design of IP and Subsystems will definitely have an edge.
Bachelors with 14+ Years or Masters with 12+ Years exp.Inside this Business Group
Xeon Performance Group (XPG) delivers custom server SoC design solutions to our data center customers. It is chartered to deliver data centric silicon that is high-performing, cost-effective, high-quality, and on schedule in way that increases market share and drives the best solutions for our customers.
Legal Disclaimer:
Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel's offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.

About Intel

Job Source : jobs.intel.com

Similar Jobs

Career Advice to Find Better